A switched capacitor circuit, including a metal-oxide-semiconductor field-effect transistor-based switch comprising: a first metal-oxide-semiconductor field-effect transistor having a gate, a source and a drain, wherein the source is connected to a first node and the drain is connected to a second node or wherein the drain is connected to the first node and the source is connected to the second node; a second metal-oxide-semiconductor field-effect transistor having a gate, a source and a drain, wherein the source is connected to the drain and the source and the drain are together connected to the second node; a first capacitor connected between the first node and a third node; and a second capacitor connected between the second node and the third node.

A sampling circuit includes a linearization circuit connected to a first input terminal for receiving a first input signal and a second input terminal for receiving a second input signal, a first switch connected between the first input terminal and the linearization circuit, a second switch connected between the first input terminal and the linearization circuit, a third switch connected between the second input terminal and the linearization circuit, a fourth switch connected between the second input terminal and the linearization circuit, a first capacitor connected between the linearization circuit and a first output terminal for outputting a first sampled signal, and a second capacitor connected between the linearization circuit and a second output terminal for outputting a second sampled signal.

A circuit can include a voltage comparator V.sub.d having a first input, a second input, and an output; a first plurality of capacitors C.sub.p[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator V.sub.d, wherein each top plate is also switchably electrically coupled with a common mode voltage V.sub.cm, and wherein each bottom plate is switchably electrically coupled between a first input voltage V.sub.inp, a reference voltage V.sub.ref, the common mode voltage V.sub.cm, and ground; a second plurality of capacitors C.sub.n[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator V.sub.d, wherein each top plate is also switchably electrically coupled with the common mode voltage V.sub.cm, and wherein each bottom plate is switchably electrically coupled between a second input voltage V.sub.inn, the reference voltage V.sub.ref, the common mode voltage V.sub.cm, and ground; and a successive approximation register (SAR) controller coupled with the output of the voltage comparator V.sub.d.

A circuit can include a voltage comparator V.sub.d having a first input, a second input, and an output; a first plurality of capacitors C.sub.p[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator V.sub.d, wherein each top plate is also switchably electrically coupled with a common mode voltage V.sub.cm, and wherein each bottom plate is switchably electrically coupled between a first input voltage V.sub.inp, a reference voltage V.sub.ref, the common mode voltage V.sub.cm, and ground; a second plurality of capacitors C.sub.n[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator V.sub.d, wherein each top plate is also switchably electrically coupled with the common mode voltage V.sub.cm, and wherein each bottom plate is switchably electrically coupled between a second input voltage V.sub.inn, the reference voltage V.sub.ref, the common mode voltage V.sub.cm, and ground; and a successive approximation register (SAR) controller coupled with the output of the voltage comparator V.sub.d.

An input sampling stage circuit includes, a precharge buffer, a precharge switch-capacitor circuit, and an input sampling capacitor. The precharge buffer is configured to buffer an input voltage. The precharge switch-capacitor circuit includes a plurality of switches, a first capacitor, and a second capacitor configured such that the first and second capacitors are connected in series during a coarse sampling time and in parallel during a fine sampling time and charge transfer time. The input sampling capacitor is configured to sample the input voltage through the precharge switch-capacitor circuit during the coarse sampling time and sample the input voltage directly during the fine sampling time.

A circuit comprises a plurality of bit lines, a global counter configured to provide a count value, a global reference source, a plurality of capacitors, a comparator, a storage element, and capacitor selector circuitry. The capacitor selector circuitry is configured to select, in dependence on the count value, one or more capacitors from the plurality of capacitors, and wherein the selection of the one or more capacitors is further in dependence on pre-coded codes receivable from an agent separate from the circuit, the pre-coded codes enabling specifying respective first and second sets of the plurality of capacitors as respective one or more capacitors having respective first and second capacitance values, the pre-coded codes further enabling specifying selection of the first set to be performed at an earlier time than selection of the second set, and the second capacitance value is more than the first capacitance value

There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

A sampling circuit includes: a first capacitor including a first terminal and a second terminal; a second capacitor including a third terminal and a fourth terminal; a first input node configured to receive a first input voltage that is one of a differential input voltage; a second input node configured to receive a second input voltage that is the other of the differential input voltage; a first switch circuit configured to be provided between the first input node and the first terminal; a second switch circuit configured to be provided between the second input node and the third terminal; a third switch circuit configured to be provided between the first terminal and the third terminal; and a fourth switch circuit configured to be provided between the second terminal and the fourth terminal.

An example apparatus includes bias control circuitry and sampling circuitry. The example sampling circuitry includes a first switch coupled to a first capacitor in series between an input voltage terminal and a common mode voltage terminal, the first switch including a first terminal coupled to the input voltage terminal. Additionally, the example sampling circuitry includes a second switch coupled to a second capacitor in series between the input voltage terminal and the common mode voltage terminal, the second switch including a first terminal coupled to the input voltage terminal. The example sampling circuitry also includes a third switch including a first terminal, a second terminal, and a control terminal, the first terminal of the third switch coupled to a power supply terminal, the second terminal of the third switch coupled between the first switch and the first capacitor, the control terminal coupled to the bias control circuitry.

There is provided an integrator including: a first order delay unit which outputs an output signal obtained by delaying a signal in accordance with an input signal; a first feedback unit which generates a first feedback signal in accordance with the output signal; a second feedback unit which generates a second feedback signal in accordance with the output signal; an addition and subtraction unit which adds and subtracts the first feedback signal and the second feedback signal, respectively, to and from the input signal, for an input to the delay unit; and a control unit which causes the second feedback unit to operate as a delay circuit during the first period, and causes the second feedback unit to operate as a gain circuit having a gain smaller than 0 during the second period.