A dynamic comparator includes a differential amplifier stage, a switching unit and a switching charge storage unit. The switching charge storage unit includes a plurality of switching transistors, and a charge storage capacitor electrically connected to the plurality of switching transistors. When an operational mode of the dynamic comparator is switched from a comparison state to a reset state, a voltage on one of a first terminal and a second terminal of the charge storage capacitor is increased from a half of the system voltage to a system voltage, so as to implement a charge recycle effect. The dynamic comparator of the present invention can have lower power consumption and lower charge-discharge current.

A touch processing circuit includes: a front-end circuit including an amplifier, a first capacitor, a second capacitor, a third capacitor, and a plurality of switches each having two ends that are selectively connected each other, the front-end circuit being configured to process an input signal varying according to a touch; and a controller controlling the plurality of switches so that the front-end circuit is configured as a first circuit that accumulates deviation of the input signal between a first phase and a second phase during an integration period and a second circuit that converts the accumulated deviation into a digital signal during a conversion period.

Disclosed herein are some examples of analog-to-digital converters (ADCs) that can perform auto-zeroing with amplifying a signal for improvement of a signal-to-noise ratio. The ADCs may produce a first digital code to represent an analog input signal and a second digital code based on a residue from the first digital code, and may combine the first digital code and the second digital code to produce a digital output code to represent the analog input signal. The ADC may utilize a first observation and a second observation of an analog residue value representing the residue to produce the second digital code.

A capacitor-based digital-to-analog-converter produces a level-shifted analog outputs by precharging respective sets of output-generating capacitors to different applied potentials and then floating a common output of the sets of capacitors such that charge is redistributed among the capacitors through the common output to yield, across all the capacitors, a uniform precharge voltage that falls between the different applied potentials.

A capacitive analog-to-digital converter, an analog-to-digital conversion system, a chip, and a device. The capacitive analog-to-digital converter includes: a first capacitor array, including N first capacitor banks that include M first capacitors, where M is a positive integer greater than N; M first switches, respectively connected to first electrode plates of the M first capacitors in a one-to-one correspondence to enable a successive approximation logic controller to control connections of the first electrode plates of the M first capacitors with an output of a voltage generation circuit and with a first sampling voltage output by controlling the M first switches; a comparator, including a first input, a second input and an output; and the successive approximation logic controller, connected to the output of the comparator, and configured to control the M first switches according to comparison results output by the output of the comparator.

A multi-stage switched capacitor circuit and an operation method thereof are provided. The multi-stage switched capacitor circuit includes a first operational stage, a second operational stage and a third operational stage that are serially connected in order. Each operational stage operates in a sample phase or a hold phase and generates a detection signal indicating an end of the hold phase. The operation method of the multi-stage switched capacitor circuit includes: controlling the second operational stage to operate in the hold phase when the detection signal of the first operational stage indicates the end of the hold phase of the first operational stage, and the detection signal of the third operational stage indicates the end of the hold phase of the third operational stage.

A LIDAR device includes an input node, an output node, and a sample-and-convert circuit. The input node receives a photodetector signal, and the output node generates an output signal indicating a light intensity value of the photodetector signal. The sample-and-convert circuit includes a number of detection channels coupled in parallel between the input node and the output node. In some aspects, each of the detection channels may be configured to sample a value of the photodetector signal during the sample mode and to hold the sampled value during the convert mode using a single capacitor.

A LIDAR device includes an input node, an output node, and a sample-and-convert circuit. The input node receives a photodetector signal, and the output node generates an output signal indicating a light intensity value of the photodetector signal. The sample-and-convert circuit includes a number of detection channels coupled in parallel between the input node and the output node. In some aspects, each of the detection channels may be configured to sample a value of the photodetector signal during the sample mode and to hold the sampled value during the convert mode using a single capacitor.

A capacitor-based digital-to-analog-converter produces a level-shifted analog outputs by precharging respective sets of output-generating capacitors to different applied potentials and then floating a common output of the sets of capacitors such that charge is redistributed among the capacitors through the common output to yield, across all the capacitors, a uniform precharge voltage that falls between the different applied potentials.

A method for testing an A/D converter with a built-in diagnostic circuit with a user supplied variable input voltage includes generating a charge by a binary-weighted capacitor array responsive to an external voltage and a user specified code. The method further includes applying the charge to a first input of a voltage comparator and applying a bias voltage to a second input of the voltage comparator, and generating, by the voltage comparator, a comparison voltage responsive to the applied charge and the bias voltage. The method also includes applying the comparison voltage to an input of a successive approximation register and generating, by the successive approximation register, an approximate digital code responsive to the comparison voltage. The method also includes determining if at least one bit of the approximate digital code fails to toggle independent of adjacent bits.