An operational amplifier includes: a first gain stage for generating a second signal based on a first signal transmitted from a prior stage circuit; a second gain stage for generating an output signal based on the second signal; multiple candidate capacitors; and a capacitor selection circuit for switching the coupling relationship of the multiple candidate capacitors based on the magnitude of an input signal of the prior stage circuit, so that only a portion of the multiple candidate capacitors could be coupled to the second gain stage at a time.

A LIDAR device includes an input node, an output node, and a sample-and-convert circuit. The input node receives a photodetector signal, and the output node generates an output signal indicating a light intensity value of the photodetector signal. The sample-and-convert circuit includes a number of detection channels coupled in parallel between the input node and the output node. In some aspects, each of the detection channels may be configured to sample a value of the photodetector signal during the sample mode and to hold the sampled value during the convert mode using a single capacitor.

The analog-to-digital converter includes a quantizer for outputting a quantized signal, a sampling circuit for sampling an analog input signal, a dithering circuit for generating an added voltage, and an integrating circuit for integrating a signal on which the added voltage is superimposed and outputting an integration result to the quantizer. The dithering circuit includes a variable capacitance circuit and a control circuit. The variable capacitance circuit includes a plurality of capacitors. The control circuit controls the capacitance of the variable capacitance circuit to a capacitance smaller than the capacitances of the capacitors, and causes the variable capacitance circuit to generate an added voltage.

The circuit device includes an integration period signal generation circuit, a polarity switching signal generation circuit, and first and second integration circuits. The integration period signal generation circuit generates a first integration period signal kept in an active state in the first integration period. The polarity switching signal generation circuit generates a first integration polarity switching signal making a transition at a timing synchronized with the reference clock signal in the first integration period, and a second integration polarity switching signal making a transition a predetermined clock count of the reference clock signal after the transition timing of the first integration polarity switching signal in the first integration period. The first integration circuit performs an integrating process in which an integration polarity is switched at the transition timing of the first integration polarity switching signal in the first integration period. The second integration circuit performs an integrating process in which an integration polarity is switched at the transition timing of the second integration polarity switching signal in the first integration period.

An all-digital operational amplifier architecture, that does not have the constraint of maintaining devices in their saturation region, can leverage the high speed achievable by deeply scaled technology to replace traditional linear current referenced continuous-time operational amplifier circuits with CMOS-like dynamic circuits that require no referencing structure, have no static power consumption, and are compatible with ultra-low supply voltages. Techniques are described to replace analog continuous-time linear operational amplifier input and output stages by a discrete-time comparator circuit, e.g., CMOS-style, and a switched capacitor charge pump circuit, respectively.

An image sensor may contain an array of imaging pixels arranged in rows and columns. Each column of imaging pixels may be coupled to a column line which is used to read out imaging signals from the pixels. The column line may be coupled to an analog-to-digital converter for converting analog imaging signals from the pixels to digital signals. The analog-to-digital converter may be implemented as a charge sharing successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include a comparator coupled to a feedback digital-to-analog converter (DAC). The comparator may have a non-zero comparator offset. The feedback DAC may include capacitors that are scaled using a sub-radix-2 sizing scheme to help improve tolerance to the comparator offset while enabling resolutions of up to 10-bits or more.

A sample-and-hold amplifier includes: a switched capacitor network for conducting a sample-and-hold operation on an input signal to generate a first signal; and an operational amplifier coupled with the switched capacitor network and including multiple candidate capacitors; wherein the operational amplifier is arranged to operably generate an output signal based on the first signal, and to operably switch coupling relationship of the multiple candidate capacitors based on the magnitude of the input signal, so that only a portion of the multiple candidate capacitors could be participated in the generation of the output signal at a time.

An analog to digital conversion apparatus that includes an analog to digital converter (ADC), a linearity calculating module and a calibration module is provided. The ADC includes a capacitor array, a comparator and a control circuit. The capacitor array receives an input signal to perform a capacitor-switching to generate a capacitor array output signal. The comparator compares the capacitor array output signal and a comparing signal to generate a digital code output result. The control circuit controls the capacitor-switching according to the digital code output result. The linearity calculating module generates a linearity related parameter according to the digital code output result. The calibration module generates a weighting parameter according to the linearity related parameter when the linearity related parameter is not within a predetermined range to adjust the digital code output result based on the weighting parameter to generate an adjusted digital code output result.

An analog-to-digital converter includes an analog-to-digital conversion unit configured to output first and second digital signals based on a comparison of first and second reference voltages with an input signal, an amplifier including first and second input terminals and an output terminal, a first capacitor having one end or electrode connected to the first input terminal of the amplifier, a second capacitor having one end or electrode connected to the first input terminal of the amplifier, a third capacitor having one end or electrode connected to the first input terminal of the amplifier, a switch unit configured to selectively provide a third or fourth reference voltage to at least one of the second and third capacitors based on the first and second digital signals, and a control switch between another end or electrode of the first capacitor and the output terminal of the amplifier.

An analog-to-digital converter includes an analog-to-digital conversion unit configured to output first and second digital signals based on a comparison of first and second reference voltages with an input signal, an amplifier including first and second input terminals and an output terminal, a first capacitor having one end or electrode connected to the first input terminal of the amplifier, a second capacitor having one end or electrode connected to the first input terminal of the amplifier, a third capacitor having one end or electrode connected to the first input terminal of the amplifier, a switch unit configured to selectively provide a third or fourth reference voltage to at least one of the second and third capacitors based on the first and second digital signals, and a control switch between another end or electrode of the first capacitor and the output terminal of the amplifier.