Methods and systems for an analog-to-digital converter with near-constant common mode voltage may comprise, in an analog-to-digital converter (ADC) having sampling switches on each input line to the ADC, N double-sided and M single-sided switched capacitors on each input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the double-sided switched capacitors between a reference voltage (Vref) and ground, and iteratively switching the single-sided switched capacitors between ground and voltages that may equal Vref/2.sup.x where x ranges from 0 to m1 and m is a number of single-sided switched capacitors per input line. A common mode offset of the ADC may be less than V.sub.ADC.sub._.sub.fs/128+V.sub.ADC.sub._.sub.fs/256+V.sub.ADC.sub._.sub.fs/512+V.sub.ADC.sub._.sub.fs/1024 when m equals 4 and where V.sub.ADC.sub._.sub.fs is the full-scale voltage of the ADC.

An analog-to-digital converter includes an input-signal chopping switch, an integrator, an output chopping switch, a quantizer, and a feedback switch. The integrator is located after the input-signal chopping switch. The integrator includes an operational amplifier, an integral capacitor, and an integral-capacitor-chopping input switch being at on an input side of the integral capacitor. The output chopping switch is on an output side of the operational amplifier. The quantizer is located after the output chopping switch. The feedback chopping switch is in a feedback path from an output of the quantizer to an input of the first integrator. The input-signal chopping switch, the integral-capacitor-chopping input switch, the output chopping switch, and the feedback chopping switch execute chopping at an identical frequency. The output chopping switch sets a polarity of an input value of the quantizer to be identical before and after the chopping.

The disclosure includes an analog to digital converter (ADC). The ADC includes a comparator to compare sample values of an analog signal in an analog domain to reference values to determine digital values in a digital domain. The digital values correspond to the analog signal and may be determined according to successive approximation. The ADC also includes chop switches to modulate the analog signal to increase a frequency of flicker noise in the analog domain. The ADC also includes an un-chop switch to demodulate the digital values in the digital domain prior filtration of the flicker noise by a digital filter.

An analog-to-digital converter (ADC) includes an analog voltage sampler having an energy storage device, such as a capacitive element, configured to charge based on an analog input voltage. A timer determines an elapsed time for the energy storage device to discharge to a predetermined value. The ADC outputs a digital value representing the analog input voltage based on the determined elapsed time.

An example SC integrator can include first and second sampling capacitors, an amplifier, an integrating capacitor, coupled at least to an output of the amplifier, and a switching arrangement. The SC integrator can be configured for adding (i.e., integrating in the integrating capacitor) sign-inverted samples of a flicker noise of the amplifier at one or more cycles of a master clock and can be configured for keeping the time distance/delay between those samples relatively small across a range of master clock frequencies.

An analog-to-digital converter (ADC) includes an analog voltage sampler having an energy storage device, such as a capacitive element, configured to charge based on an analog input voltage. A timer determines an elapsed time for the energy storage device to discharge to a predetermined value. The ADC outputs a digital value representing the analog input voltage based on the determined elapsed time.

The disclosure includes a mechanism for mitigating charge related disturbances in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by providing a fine reference connection and a rough reference connection. A switch array is activated to couple a current bit capacitor of a capacitor array to the rough reference connection while a current bit corresponding to the current bit capacitor is determined by a comparator. The switch array is further activated to couple a previous bit capacitor of the capacitor array to the fine reference connection while the current bit capacitor is coupled to the rough reference connection. This separates charge flow on the rough reference connection from capacitors coupled to the fine reference connection.

Methods and systems for an analog-to-digital converter with near-constant common mode voltage may comprise, in an analog-to-digital converter (ADC) having sampling switches on each input line to the ADC, N double-sided and M single-sided switched capacitors on each input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the double-sided switched capacitors between a reference voltage (Vref) and ground, and iteratively switching the single-sided switched capacitors between ground and voltages that may equal Vref/2.sup.x where x ranges from 0 to m1 and m is a number of single-sided switched capacitors per input line. A common mode offset of the ADC may be less than V.sub.ADC.sub._.sub.fs/128+V.sub.ADC.sub._.sub.fs/256+V.sub.ADC.sub._.sub.fs/512+V.sub.ADC.sub._.sub.fs/1024 when m equals 4 and where V.sub.ADC.sub._.sub.fs is the full-scale voltage of the ADC.

A comparison method includes: providing a successive approximation register analog-to-digital converter, where the successive approximation register analog-to-digital converter includes n?1 weighted capacitors, a charge transfer capacitor, and a comparator; sampling an differential input signal by using the first weighted capacitor and the charge transfer capacitor; importing the differential input signal stored on the charge transfer capacitor, where the differential input signal is transferred and redistributed on the charge transfer capacitor and n?2 other weighted capacitors than the first weighted capacitor, and completing the first time of comparison; and importing the differential input signal stored on the first weighted capacitor and the differential input signal stored on the charge transfer capacitor, importing a reference voltage by using the second to jth weighted capacitors, where the differential input signal and the reference voltage are transferred and redistributed on a capacitor array, and completing a jth time of comparison.

An analog-to-digital converter of non-binary capacitor array with redundancy bits and its chip. The non-binary capacitor array with redundancy bits comprises a common-mode voltage, analog signal input, no less than one redundancy bit capacitor and multiple capacitors; each capacitor of capacitors with redundancy bits and multiple capacitors is connected in parallel between common-mode voltage and analog signal input and marked in a sequence from highest to lowest/lowest to highest bit; the sum of the capacitance of capacitors from the lowest bit capacitor to an random capacitor must be no less than the capacitance of the higher bit capacitor adjacent to the random capacitor. The ratio of the capacitance of each capacitor to the capacitance of unit capacitor is set to be positive. The capacitor array is applied into an analog-to-digital converter or fabricated as a chip.