A self-calibrating analog-to-digital converter includes a reference signal circuit configured to provide a reference signal, an analog-to-digital converter configured to generate a first digital representation of the reference signal, a dual-slope analog-to-digital converter configured to generate a second digital representation of the reference signal, and a digital engine configured to compare the first digital representation with the second digital representation to obtain a difference and output a calibration signal to the analog-to-digital converter in response to the difference. The reference signal circuit, the analog-to-digital converter, the dual-slop analog-to-digital converter, and digital engine are integrated in an integrated circuit.

A non-linear converter comprising a non-linear voltage divider having a plurality of resistors representing a non-linear transfer function, an analog multiplexer having analog multiplexer inputs coupled to the non-linear voltage divider and configured to output an analog multiplexer output, the analog multiplexer chooses one of the plurality of resistors based on a logic signal and the non-linear transfer function, an analog comparator having an analog comparator first input configured to receive an analog input voltage, an analog comparator second input configured to receive the analog multiplexer output and the analog comparator configured to output a comparator voltage output and a logic loop coupled to the analog comparator and configured to receive the comparator voltage output and configured to output the logic signal, wherein the logic signal represents a linearized digital word.

In accordance with an embodiment, a method of monitoring a data converter includes determining a multiplicity of time-associated linearity parameters that describe a linearity of the data converter at a multiplicity of different times, and determining a state of the data converter based on comparing at least one linearity parameter of the multiplicity of time-associated linearity parameters with a comparison parameter.

An analog to digital converter (ADC) senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. The digital output signal provided to the N-bit DAC is an inverse function of the load current. The ADC is operative to sense very low currents (e.g., currents as low as is of pico-amps) and consume very little power (e.g., less than 2 ?W).

A non-linear converter comprising a non-linear voltage divider having a plurality of resistors representing a non-linear transfer function, an analog multiplexer having analog multiplexer inputs coupled to the non-linear voltage divider and configured to output an analog multiplexer output, the analog multiplexer chooses one of the plurality of resistors based on a logic signal and the non-linear transfer function, an analog comparator having an analog comparator first input configured to receive an analog input voltage, an analog comparator second input configured to receive the analog multiplexer output and the analog comparator configured to output a comparator voltage output and a logic loop coupled to the analog comparator and configured to receive the comparator voltage output and configured to output the logic signal, wherein the logic signal represents a linearized digital word.

Methods and systems for analog-to-digital conversion using two side branches that may be operated with overlapped timing such that a sampling phase may be overlapped with a previous conversion phase. Some embodiments provide a method of successive approximation A/D converting, comprising sampling a first signal onto a first capacitor that is configured to selectively couple to an analog input of a comparator, sampling a second signal onto capacitors that are coupled to a second analog input of the comparator and configured for charge redistribution successive approximation A/D conversion; carrying out, based on the first signal and the second signal, a charge redistribution successive approximation A/D conversion using the capacitors; and while carrying out the charge redistribution successive approximation A/D conversion based on the first and second signals, sampling a third signal onto a third capacitor that is configured to selectively couple to the analog input of a comparator.

A self-calibrating analog-to-digital converter includes a reference signal circuit configured to provide a reference signal, an analog-to-digital converter configured to generate a first digital representation of the reference signal, a dual-slope analog-to-digital converter configured to generate a second digital representation of the reference signal, and a digital engine configured to compare the first digital representation with the second digital representation to obtain a difference and output a calibration signal to the analog-to-digital converter in response to the difference. The reference signal circuit, the analog-to-digital converter, the dual-slop analog-to-digital converter, and digital engine are integrated in an integrated circuit.

Methods and systems for analog-to-digital conversion using two side branches that may be operated with overlapped timing such that a sampling phase may be overlapped with a previous conversion phase. Some embodiments provide a method of successive approximation A/D converting, comprising sampling a first signal onto a first capacitor that is configured to selectively couple to an analog input of a comparator, sampling a second signal onto capacitors that are coupled to a second analog input of the comparator and configured for charge redistribution successive approximation A/D conversion; carrying out, based on the first signal and the second signal, a charge redistribution successive approximation A/D conversion using the capacitors; and while carrying out the charge redistribution successive approximation A/D conversion based on the first and second signals, sampling a third signal onto a third capacitor that is configured to selectively couple to the analog input of a comparator.

A non-linear converter comprising a non-linear voltage divider having a plurality of resistors representing a non-linear transfer function, an analog multiplexer having analog multiplexer inputs coupled to the non-linear voltage divider and configured to output an analog multiplexer output, the analog multiplexer chooses one of the plurality of resistors based on a logic signal and the non-linear transfer function, an analog comparator having an analog comparator first input configured to receive an analog input voltage, an analog comparator second input configured to receive the analog multiplexer output and the analog comparator configured to output a comparator voltage output and a logic loop coupled to the analog comparator and configured to receive the comparator voltage output and configured to output the logic signal, wherein the logic signal represents a linearized digital word.

A non-linear converter comprising a non-linear voltage divider having a plurality of resistors representing a non-linear transfer function, an analog multiplexer having analog multiplexer inputs coupled to the non-linear voltage divider and configured to output an analog multiplexer output, the analog multiplexer chooses one of the plurality of resistors based on a logic signal and the non-linear transfer function, an analog comparator having an analog comparator first input configured to receive an analog input voltage, an analog comparator second input configured to receive the analog multiplexer output and the analog comparator configured to output a comparator voltage output and a logic loop coupled to the analog comparator and configured to receive the comparator voltage output and configured to output the logic signal, wherein the logic signal represents a linearized digital word.