Disclosed are a capacitance-to-digital conversion circuit, a capacitance-to-digital conversion method and an electronic chip. The capacitance-to-digital conversion circuit includes a first module, a comparator and an adaptive range-shift module; the first module includes a successive approximation unit, a first adder, a first digital-to-analog converter, a second adder, a third adder and an integrating unit. The first module further includes a second digital-to-analog converter connected to the third adder. The comparator, the adaptive range-shift module and the first adder are connected in series and the comparator is connected to the second digital-to-analog converter. By the present application, the adverse influence caused by the parasitic and interference is well avoided, the capacitance-to-digital conversion circuit may work in a harsh environment, the robustness of the circuit is significantly improved and the application range of the circuit is expanded.

A Unit Element (UE) has a positive UE and a negative UE, each having a digital X input and a digital W input with a sign bit, the sign bit is exclusive ORed with a chop clock to generate a chopped sign bit. The positive UE is enabled when the chopped sign bit is positive and the negative UE is enabled when the chopped sign bit is negative. Each positive and negative UE comprises groups of NAND gates generating an output and complementary output which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The NAND gate outputs and complementary outputs are coupled through binary weighted charge transfer capacitors the positive charge transfer line and negative charge transfer line.

A Bias Unit Element (UE) has a digital input, a sign input, and a chop clock. The sign input is exclusive ORed with the chop clock to generate a signed chop clock. Each Bias UE comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The chopped sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.

A Bias Unit Element (UE) has a digital input and sign input, and comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.

An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspect of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor to form an analog multiplication product as a charge applied to the differential charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.

A Unit Element (UE) has a digital X input and a digital W input, and comprises groups of NAND gates generating complementary outputs which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The number of bits in the X input determines the number of NAND gates in a NAND-group and the number of bits in the W input determines the number of NAND groups. Each NAND-group receives one bit of the W input applied to all of the NAND gates of the NAND-group, and each unit element having the bits of X applied to each associated NAND gate input of each unit element. The NAND gate outputs are coupled through binary weighted charge transfer capacitors to a positive charge transfer line and negative charge transfer line.

An architecture for a chopper stabilized multiplier-accumulator (MAC) uses a chop clock and common Unit Element (UE), the MAC formed as a plurality of MAC UEs receiving X and W values and a sign bit exclusive ORed with the chop clock, a plurality of Bias UEs receiving E value and a sign bit exclusive ORed with the chop clock, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.

A Gain Balanced Analog Multiply-Accumulator (AMAC) has an inference memory which outputs subsets of inference data comprising X input values and one or more associated W coefficient values. The Gain Balanced AMAC has a number of Analog Multiplier-Accumulator Unit Elements (AMAC UE) in equal number to the number of X input values in each subset of inference data. In each of a series of multiply-accumulate cycles, the X input values and one or more W coefficient values from the inference memory are applied to each AMAC UE to generate a charge corresponding to the multiplication of X input value and W coefficient value of each AMAC UE which is transferred to a shared analog charge bus. The inference memory applies the X input value and W coefficient values of each subset to a different AMAC UE on subsequent cycles to balance the gain of the AMAC such that gain differences from one AMAC UE to another are not cumulative.

Provided are an analog-to-digital converter and/or an operating method thereof. The analog-to-digital converter includes a sample/hold circuit, a digital-to-analog converter, a comparing circuit, and a control logic circuit, wherein the digital-to-analog converter includes a first capacitor connected to a first comparison node and a first filtering node, a first reference voltage switch connected to the first filtering node and connected to a first delivery node or a first transmission node, a first pre-charge switch connected to the first filtering node or the first delivery node, and a first pre-charge capacitor connected to the first pre-charge switch and a ground voltage.

A circuit includes an amplifier having first and second inputs and an output, and a feedback circuit configured to generate a feedback voltage in response to a voltage at the output of the amplifier. The feedback circuit is coupled to the first input of the amplifier to provide the feedback voltage to the first input of the amplifier. An output circuit is configured to generate a variable bias current in response to the voltage at the output of the amplifier. A switch circuit is configured to switch the second input of the amplifier from receiving a first reference voltage during a first mode of operation to receiving a second reference voltage during a second mode of operation.