An exemplary quantizer includes a multi-bit analog-to-digital converter (ADC) and a first digital-to-analog converter (DAC) feedback circuit. The multi-bit ADC has an internal DAC associated with comparison of each sampled analog input of the multi-bit ADC. The multi-bit ADC converts a currently-sampled analog input into a first digital output. A first noise-shaped truncation output is derived from the first digital output. The first DAC feedback circuit transfers a first truncation residue associated with the first noise-shaped truncation output to the internal DAC. The transferred first truncation residue is reflected in comparison of a later-sampled analog input of the multi-bit ADC via the internal DAC.

A successive approximation Analogue to Digital Converter (ADC), comprising: a sample and hold device arranged to sample and hold an input signal at the beginning of a conversion cycle; a successive approximation register that sequentially builds up a digital output from its most significant bit to its least significant bit; a digital to analogue converter that outputs a signal based on the output of the successive approximation register; a comparator that compares the output of the digital to analogue converter with an output of the sample and hold device and supplies its output to the successive approximation register; and a residual signal storage device arranged to store the residual signal at the end of a conversion cycle; and wherein the successive approximation ADC is arranged to add the stored residual signal from the residual signal storage device to the input signal stored on the sample and hold device at the start of each conversion cycle. After each ADC full conversion by the SAR, the analogue conversion of the digital output is as close to the original input signal as the resolution will allow. However there remains the residual part of the input signal that is smaller than what can be represented by the least significant bit of the digital output of the SAR. In normal operation, successive outputs of a SAR for the same input will result in the same digital value output and the same residual. By storing the residual at the end of each conversion and adding the residual onto the input signal of the next conversion the residuals are accumulated over time so that they may affect the output digital value. After a number of conversions, the accumulated residuals add up to more than the value represented by the LSB of the register and the digital value will be one higher than if a conversion had been performed on the input signal alone. In this way, the residual signal affects the output value in time and thus can be taken into account by processing the digital output in the time domain.

An A/D converter includes an A/D conversion unit and an output unit. The A/D conversion unit includes a second A/D converter (successive approximation register A/D converter) and generates first digital data having a first number of bits and second digital data having a second number of bits, where the second number of bits is smaller than the first number of bits. The output unit provides first output information that is the first digital data and also provides second output information based on the second digital data. The output unit provides the second output information before providing the first output information.

One or more embodiments of a successive approximation type analog-to-digital converter that converts an analog input into a digital conversion value and outputs the digital conversion value, may include: a capacitance DAC that generates a bit-by-bit potential based on an analog input; a comparator that compares the potential generated by the capacitance DAC, wherein the comparator is a memory cell rewriting type, the comparator includes a first stage current mirror type operational amplifier; and a second stage memory cell; a conversion data generator that generates conversion data of resolution bits based on a comparison result of the comparator; and a correction circuit that corrects an output error of the conversion data caused by an offset error of the comparator by adding or subtracting an offset correction value that is a fixed value, and outputs the conversion data as a digital conversion value.

In an example embodiment, an apparatus includes: a first sampling capacitor and a comparator to compare a sum voltage at a first input terminal to a voltage level at a second input terminal according to a thermometer cycle. The sum voltage is based at least in part on an analog input voltage and a divided reference voltage, where the analog input voltage and the reference voltage (V.sub.REF) are of a first voltage range and the divided reference voltage is according to $\left(\left(2^M-1\right)V_{\mathrm{REF}}/2^M\right),$
to enable the comparator to operate at a second voltage range, the second voltage range less than $V_{\mathrm{REF}}/2^M,$
and M is a number of bits of a digital output to be decided in the thermometer cycle and is greater than one.

A kickback current is suppressed so as not to generate a deviation in a signal that outputs a comparison result.

A comparator includes a first input terminal and a second input terminal to which a first differential input signal pair is input, a third input terminal and a fourth input terminal to which a second differential input signal pair is input, a first comparison circuit that outputs a signal corresponding to a difference signal of the first differential input signal pair generated by connecting the first input terminal to a positive side and connecting the second input terminal to a negative side and a difference signal of the second differential input signal pair generated by connecting the third input terminal to a positive side and connecting the fourth input terminal to a negative side, and a second comparison circuit that outputs a signal corresponding to a difference signal of the first differential input signal pair generated by connecting the first input terminal to a negative side and connecting the second input terminal to a positive side, and a difference signal of the second differential input signal pair generated by connecting the third input terminal to a positive side and connecting the fourth input terminal to a negative side.

A method of operating an analog-to-digital converter includes in a first sampling stage, switching a swap signal to a first level for a first selection circuit to reset a first capacitor array according to a first voltage configuration and for a second selection circuit to reset a second capacitor array according to the first voltage configuration, and in a second sampling stage, switching the swap signal to a second level for the first selection circuit to reset the first capacitor array according to the second voltage configuration and for the second selection circuit to reset the second capacitor array according to the second voltage configuration. A control logic circuit is used to switch the swap signal between the first level and the second level in a uniform order in a plurality of sampling stages.

A differential subrange analog-to-digital converter (ADC) converts differential analog image signals received from sample and hold circuits to a digital signal through an ADC comparator. The comparator of the differential subrange ADC is shared by a successive approximation register (SAR) ADC coupled to provide both M upper output bits (UOB) and a ramp ADC coupled to provide N lower output bits (LOB). Digital-to-analog converters (DACs) of the differential subrange SAR ADC comprises 2M buffered bit capacitor fingers connected to the comparator. Each buffered bit capacitor finger comprises a bit capacitor, a bit buffer, and a bit switch controlled by the UOB. Both DACs are initialized to preset values and finalized based on the values of the least significant bit of the UOB. The subsequent ramp ADC operation will be ensured to have its first ramp signal ramps in a monotonic direction and its second ramp signal ramp in an opposite direction.

A calibration method for a digital-to-analog converter (DAC) is disclosed. The DAC is applied to a successive approximation analog-to-digital converter (SA ADC) and includes a first capacitor, multiple second capacitors and a bridge capacitor. The method includes the steps of: (a) controlling voltages at two input terminals of a comparator of the SA ADC to be equal; (b) changing a voltage at a first terminal of the first capacitor; (b) obtaining a first output of the SA ADC; (d) after obtaining the first output, controlling voltages at the two input terminals of the comparator to be equal; (e) changing voltages at multiple first terminals of the second capacitors; (f) obtaining a second output of the SA ADC; and (g) calibrating the DAC according to the first output and the second output.

An analog-to-digital converter, configured to convert an input signal into an n bits digital output signal, includes a capacitor module, a control signal generation unit, a comparator, and a register. The capacitor module is configured to receive the input signal at a sampling phase in a normal mode, and to generate a first sampling signal and a second sampling signal according to the input signal in a conversion phase. The control signal generation unit is configured to adjust the first sampling signal or the second sampling signal in the conversion phase. In the normal mode, the comparator is configured to compare the first sampling signal and the second sampling signal in the conversion phase to generate n comparison signals. The register is configured to store the n comparison signals as the digital output signal, and output the digital output signal in the normal mode.