Certain aspects of the present disclosure provide a successive approximation register (SAR) analog-to-digital converter (ADC) implemented with a digital filter for noise shaping. For example, certain aspects provide a circuit for analog-to-digital conversion having: a first digital-to-analog converter (DAC) having an output coupled to a sampling node; a comparator having an input coupled to the sampling node; SAR logic having an input coupled to an output of the comparator and at least one output coupled to an input of the first DAC; a quantizer configured to generate a first digital signal representing a voltage at the sampling node; a digital filter configured to apply a filter to the first digital signal; and a second DAC configured to generate an analog signal representing the filtered first digital signal and provide the analog signal to the sampling node.

A method of using an analog-to-digital converter system includes receiving a sampled voltage corresponding to one of an input voltage and a known voltage, causing preamplifiers to generate output signals based on the sampled voltage, generating first and second signals based on the output signals, causing a delay-resolving delay-to-digital backend to generate a single-bit digital signal representing an order of receipt of the first and second signals, and adjusting one or more of the preamplifiers based on the digital signal. The disclosure also relates to a system which includes a voltage-to-delay frontend and a delay-resolving backend, and to a method which includes causing a delay comparator to generate a single-bit digital signal representing an order of receipt of input signals, causing the comparator to transmit a residue delay signal to a succeeding comparator, and transmitting a signal to adjust one or more of the preamplifiers based on the digital signal.

The present description relates to a comparator (2) comprising a ring of gates (110A, 110B, 110A′, 110B′, 106, 108) in series, wherein: each gate implements an inverting function between a first input (100) and an output (102) of the gate; at least one (110A′, 110B′) gate is controllable and is associated with another gate; each controllable gate (110A′, 110B′) comprises a control input (116) coupled with the output (102) of said associated gate, and prevents switching of its output (102) to a high state if its control input (116) is in the high state, and to a low state otherwise; and the control input (116) of each controllable gate (110A′, 110B′) receives the output (102) of said associated gate if an even number of gates separates these two gates, and receives the complement of said output if not.

A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.

A digital-to-analog conversion circuit (60) for converting a digital input sequence to an analog representation is disclosed. It comprises a first DAC, (100) wherein the first DAC (100) is of a capacitive voltage division type having a capacitive load (110). Furthermore, it comprises a second DAC (120) having a resistive load (130). An output (104) of the first DAC (100) and an output (124) of the second DAC (120) are connected, such that said capacitive load (110) and said resistive load (130) are connected in parallel.

A semiconductor device performs sequential comparison of an analog input signal and a reference voltage to digitally convert the analog input signal. The semiconductor device includes an upper DAC generating a high-voltage region of the reference voltage based on a predetermined code, a lower DAC generating a low-voltage region of the reference voltage based on the code, and an injection DAC having the same configuration as that of the lower DAC and adjusting the low-voltage region of the reference voltage.

A reference voltage controlling circuit and an analog-to-digital converter are disclosed. The reference voltage controlling circuit includes a reference voltage generating circuit, a plurality of groups of sampling switching units and a logic controlling circuit. The DAC capacitor array switches the sampling switching units to a second positive reference voltage and a second negative reference voltage before starting sampling or conversion, and is charged and discharged with the second positive reference voltage and the second negative reference voltage to raise a voltage to a preset voltage. The sampling switching unit is switched to a first positive reference voltage and a first negative reference voltage to charge and discharge the DAC capacitor array to a target voltage. The rising of the voltage from the preset voltage to the target voltage is completed by the first positive reference voltage and the first negative reference voltage.

A reference voltage buffer circuit is provided, which could improve the reliability of the reference voltage buffer circuit, including: at least one output branch, where each output branch includes a delay control branch, a first MOSFET, and a second MOSFET; and a feedback branch, where in a first time period, the feedback branch is configured to output a first voltage to the delay control branch, and the delay control branch is configured to control the first MOSFET and the second MOSFET to be turned on, such that a source of the first MOSFET continuously outputs a reference voltage; and in a second time period, a voltage output from the feedback branch to the delay control branch is 0, the delay control branch is configured to control the second MOSFET to be turned off before the first MOSFET is turned off.

A method of operation of a semiconductor device that includes the steps of coupling each of a plurality of digital inputs to a corresponding row of non-volatile memory (NVM) cells that stores an individual weight, initiating a read operation based on a digital value of a first bit of the plurality of digital inputs, accumulating along a first bit-line coupling a first array column weighted bit-line current, in which the weighted bit-line current corresponds to a product of the individual weight stored therein and the digital value of the first bit, and converting and scaling, an accumulated weighted bit-line current of the first column, into a scaled charge of the first bit in relation to a significance of the first bit.

A method of an electronic device includes: providing a capacitive digital-to-analog converter having a reference voltage input; providing a reference voltage providing circuit to generate a reference voltage to the reference voltage input of the capacitive digital-to-analog converter; and, generating a compensation signal into the reference voltage input of the capacitive digital-to-analog converter in response to at least one switching of at least one capacitor in a switchable capacitor network of the capacitive digital-to-analog converter.