An analog-to-digital converter and a thermopile array. The analog-to-digital converter comprises: a reference voltage generation circuit comprising a voltage generation unit; a chopping modulation unit used to perform chopping modulation on a voltage signal generated by the voltage generation unit, and to modulate low frequency noise of the voltage signal into high frequency noise; and a low-pass filter used to eliminate the high frequency noise to obtain a reference voltage. The invention employs a simple structure to obtain a low noise reference voltage at low costs.

A digital phase-locked loop (DPLL) may include a dithering source to provide a dithering signal that is on an order of up to one integer bit on a set of fractional bits of a modulation signal. The DPLL may include a digitally controlled oscillator (DCO) to generate a DPLL output signal. The DPLL may include a primary delta-sigma modulator (DSM) to drive a primary capacitor bank of the DCO based on the dithering signal and the modulation signal, a first auxiliary DSM to drive a first auxiliary capacitor bank of the DCO based on the dithering signal in association with cancelling an effect of the dithering signal on the DPLL output signal, and a second auxiliary DSM to drive a second auxiliary capacitor bank of the DCO based on the modulation signal and the dithering signal in association with cancelling an effect of a quantization error of the primary DSM.

A digital phase-locked loop (DPLL) may include a dithering source to provide a dithering signal that is on an order of up to one integer bit on a set of fractional bits of a modulation signal. The DPLL may include a digitally controlled oscillator (DCO) to generate a DPLL output signal. The DPLL may include a primary delta-sigma modulator (DSM) to drive a primary capacitor bank of the DCO based on the dithering signal and the modulation signal, a first auxiliary DSM to drive a first auxiliary capacitor bank of the DCO based on the dithering signal in association with cancelling an effect of the dithering signal on the DPLL output signal, and a second auxiliary DSM to drive a second auxiliary capacitor bank of the DCO based on the modulation signal and the dithering signal in association with cancelling an effect of a quantization error of the primary DSM.