A dynamic-zoom analog to digital converter (ADC) having a coarse flash ADC and a fine passive single-bit modulator is disclosed. Radio frequency (RF) devices incorporating aspects of the present disclosure may support multiple wireless modes operating at different frequencies. Therefore, the RF devices have need for an ADC which is flexible and optimizable in terms of resolution, bandwidth, and power consumption. In this regard, the RF devices incorporate circuits, such as ADC circuits, which incorporate a discrete-time passive delta-sigma modulator. In order to improve the resolution of the delta-sigma modulator, a coarse ADC is deployed as a zooming unit to a single-bit passive delta-sigma modulator to provide a coarse digital conversion. Coarse conversion is used to dynamically update reference voltages at an input of the delta-sigma modulator using a multi-bit feedback digital to analog converter (DAC). The dynamic-zoom ADC supports multiple modes with improved power and quantization noise.

A DAC, for use in an iADC, is configured for converting a multi-bit word to an analog feedback signal. The DAC comprises a MMS logic block. It further comprises a plurality of output elements configured to generate respective analog portions based on a selection vector and a signal combiner for combining the analog portions to the analog feedback signal. In the MMS logic block switching blocks are arranged cascaded. Each switching block receives at least a portion of the multi-bit word, splits the portion into two sub-portions and forwards them to one subsequent switching block or to one output element. A weight factor is adjusted by multiplying it with the difference of the two sub-portions. A weight accumulator accumulates successive adjusted weight factors, wherein the way of splitting the portion of a further multi-bit word is determined based on the sign of the weight accumulator.

A dynamic-zoom analog to digital converter (ADC) having a coarse flash ADC and a fine passive single-bit modulator is disclosed. Radio frequency (RF) devices incorporating aspects of the present disclosure may support multiple wireless modes operating at different frequencies. Therefore, the RF devices have need for an ADC which is flexible and optimizable in terms of resolution, bandwidth, and power consumption. In this regard, the RF devices incorporate circuits, such as ADC circuits, which incorporate a discrete-time passive delta-sigma modulator. In order to improve the resolution of the delta-sigma modulator, a coarse ADC is deployed as a zooming unit to a single-bit passive delta-sigma modulator to provide a coarse digital conversion. Coarse conversion is used to dynamically update reference voltages at an input of the delta-sigma modulator using a multi-bit feedback digital to analog converter (DAC). The dynamic-zoom ADC supports multiple modes with improved power and quantization noise.

An analog-to-digital converter circuit comprises code-shuffling circuitry, a plurality of digital-to-analog converter circuits, a plurality of difference circuits, and a plurality of latch circuits. The code-shuffling circuitry is operable to shuffle a plurality of digital codes among a plurality of its outputs. The plurality of digital-to-analog converter circuits are operable to convert a digital code on the respective one of the outputs to a corresponding one of a plurality of analog reference voltages. The plurality of difference circuits is operable to generate a respective one of a plurality of difference signals corresponding to a difference between an input voltage and a respective one of the plurality of reference voltages. The plurality of latch circuits is operable to latch a respective one of the plurality of difference signals to a corresponding one of a plurality of digital values.

An analog-to-digital conversion (ADC) system includes a transconductance amplifier, loop filter, quantizer, logic circuit, and digital-to-analog converter (DAC). The transconductance amplifier is configured to generate a current signal in response to an audio signal. The loop filter is connected to the transconductance amplifier and configured to generate a filtered signal based on the current signal. The quantizer is configured to generate a digital representation of the filtered signal. The logic circuit is configured to generate control signals based on the digital representation. The DAC is coupled to the loop filter's and the transconductance amplifier's output. The DAC includes three-level unit elements, where each unit element is configured to provide one of two signal levels or no signal to the loop filter in response to control signals from the logic circuit. Such an ADC system may allow for a high dynamic range while maintaining low power consumption and low noise.

A continuous time delta sigma modulator is disclosed. In one example, the continuous time delta sigma modulator includes: a quantizer, a buffer module, a randomizer, and a reference module. The quantizer includes a comparator that generates a digital output based on a comparison of a reference potential with an input generated based on a sample of an analog signal. The buffer module stores the digital output for a predetermined delay period and outputs the digital output after the predetermined delay period as a delayed digital output. The randomizer randomizes the delayed digital output to generate a randomized digital output. The reference module modifies the reference potential based on the randomized digital output.

A device (e.g., SAR ADC device) include a DAC circuit and generates a digital output based on logic circuitry that includes SAR logic. Additional logic circuitry includes delta modulation circuitry and dynamic element matching circuitry. The delta modulation circuitry provides several digital outputs of the SAR DAC, while the dynamic element matching circuitry selects a different set of capacitors from the DAC circuit. Each cycle is added together and averaged, and then added to the digital output from the SAR logic.

An audio digital-to-analog converter (DAC) achieves high dynamic range with low power consumption using a segmented DAC, also referred to as a noise shaped splitter. The noise shaped splitter is dynamically reconfigured based on envelope detection that tracks the amplitude of an n-bit digital input signal to the segmented DAC. The amplitude of the n-bit digital input signal can be expressed as the magnitude of a numerical value corresponding to the n bits of the digital signal. Based on the amplitude of the digital input signal, certain segments of the segmented DAC are bypassed and the components of each bypassed segment are turned off, saving power and reducing noise, and achieving improved dynamic range along with lower power consumption.

A sigma-delta modulator. The signal-delta modulator includes: an integrator having an instrumentation amplifier designed to receive an input signal to be modulated at a first input and to receive a feedback signal at a second input, wherein the integrator is designed to generate an integrator signal using the input signal and the feedback signal; a quantizer, which is designed to generate a quantizer signal in accordance with the integrator signal; a first FIR digital-to-analog converter, which is designed to generate the feedback signal in accordance with the quantizer signal; a first compensation device, which is designed to compensate for an excess loop delay in accordance with the quantizer signal; and a second compensation device, which comprises a second FIR digital-to-analog converter, which is designed to compensate for a clock cycle shift of the feedback signal in accordance with the quantizer signal.

The present invention discloses an implementation method and a device of a multi-bit - modulation-based digital speaker system. The method comprises, 1) digital format converting; 2) oversampling interpolation filtering; 3) multi-bit - modulating; 4) thermometer coding; 5) multi-channel mismatch shaping; 6) coding format converting; 7) multi-channel digital power-amplifying; 8) driving a speaker array or a multiple voice coil speaker to sound. The device comprises: a digital input interface, an oversampling interpolation filter, a multi-bit - modulator, a thermometer coder, a multi-channel mismatch shaper, a coding format converter, a multi-channel digital power-amplifier, and a speaker array or a multiple voice coil speaker; each portion being connected in proper order. The present invention can achieve a high-power output under a low-voltage power supply, save power consumption, implement a single-chip integration of a multi-channel reproducing system, reduce the volume and weight of the system and the implementing cost, and improve the quality of the reproduced sound.