The invention to mismatch and ISI shaping in a data converter. The invention provides a dynamic element matching technique that incorporates both mismatch and inter symbol interference shaping. A digital decoder is provided that controls the number of on and off transitions so that the resulting signal does not contain noise or distortion. The element selection technique of the invention is suitable for high resolution multi-bit continuous time oversampling data converters.

An RF transmitter module for a cellular radio that includes a delta-sigma modulator having a plurality of interleaving dynamic element matching (DEM) circuits providing interleaved digital bits at a reduced clock rate. An interleaver controller controls the DEM circuits so as to provide groups of the digital bits at different points in time. In one embodiment, a summation junction adds the groups of the digital bits to provide a continuous stream of the interleaved digital bits, a DAC converts the stream of interleaved digital bits to an analog signal, and a power amplifier amplifies the analog signal.

In some embodiments, an analog-to-digital converter (ADC) architecture can be implemented to process a signal from a charge output sensor. The ADC architecture can include a summing node for receiving a sensor signal from the charge output sensor, and an output node implemented to provide a digital signal representative of the sensor signal. The ADC architecture can further include a charge amplifier implemented to receive an analog signal from the summing node as an input analog signal and generate an output analog signal with a gain, and an ADC circuit implemented to generate the digital signal based on the output analog signal from the charge amplifier. The ADC architecture can further include a feedback circuit implemented between the output node and the summing node.

A system and method of digital to analog conversion including modulating a digital value D.sub.N-K with an oversampling delta sigma modulator to provide an M-bit coarse quantized value DM, in which D.sub.N-K comprises N-K least significant bits of an N-bit digital input value D.sub.N and in which quantization error may be shaped to a higher frequency above a signal band of interest, adding D.sub.M to a value D.sub.K to provide a select value D.sub.KM in which D.sub.K includes the K remaining most significant bits of D.sub.N, and applying mismatch shaping of a total of at least P=2.sup.K elements of a P-element DAC per cycle based on D.sub.KM to provide an analog output value. The analog output value may be filtered with a low-pass filter to provide a filtered analog output value. An order of low-pass filtering may be one more than an order of modulating.

A charge analog-to-digital converter (ADC) for processing a signal from a micro electrical mechanical sensor (MEMS) sensor can include a pre-amplifier integrated into a feedback loop of a delta sigma modulator to provide a reduced power consumption configuration for processing of the signal from the MEMS sensor.