A circuit includes an operational amplifier and a resistor network coupled to an output of the operational amplifier. The resistor network includes a first set of resistors coupled between the output of the operational amplifier and a first node of the resistor network, wherein the resistors of the first set are electrically connected in series with each other, a second set of resistors coupled between the first node and a second node of the resistor network, wherein the resistors of the second set are electrically connected in series with each other and include a first number of resistors, a third set of resistors coupled between the second node and a third node of the resistor network, wherein the third node is coupled to a first voltage, and wherein the resistors of the third set are electrically connected in parallel with each other and include a second number of resistors, and a resistor coupled between the first node and the second node and arranged in parallel with the second set of resistors.

Switching circuits controllable to force an input into a circuit and to sense a responsively produced output in multiple ways to produce different combinations of positive and negative polarities of a desired signal and of sources of offsets and 1/f noise. The switching circuits are controlled in a non-ordered time sequence of different combinations of positive and negative polarities of the sources of the offsets and 1/f noise that spreads their energy to a frequency range above the desired signal frequency band. The non-ordered time sequence leaves the polarity of the desired signal unchanged. Uncorrelated delta-sigma modulators may generate the control signal. A DSP processes a resulting spectrum of a digital domain version of the sensed output to measure residual offsets and 1/f noise and adds to an input present at the DSMs a signal equal in magnitude and opposite in sign to the measured residual offsets and 1/f noise.

Described is an apparatus which comprises: a first integrator to receive an input signal and to generate a first output; a second integrator to receive the first output or a version of the first output and to generate a second output; and an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit to detect an overload condition in the second output.

A D/A conversion circuit includes: an output terminal connected to an operational amplifier connected to a quantization circuit; a DAC capacitor; a selection switch switching among reference, first and second voltages to apply to the DAC capacitor as an analog potential; a ground switch connecting the DAC capacitor to a ground; and an output switch connecting the DAC capacitor to the output terminal. In a first period, the selection switch selects one of the reference, first and second voltages according to a quantization result value from the quantization circuit, and connects the one to the DAC capacitor, and the ground switch turns on to charge the DAC capacitor. In a second period, the selection switch selects another one of the first and second voltages, and connects the another one to the DAC capacitor, and the output switch turns on to output the analog potential to the output terminal.

Methods adapted for digital-to-analog conversion compensation and systems are described. In a compensation method, inputs of a digital-to-analog converter (DAC) are adjusted to provide an even number inputs for the DAC. Further, one or more analog input signals are converted to generate one or more corresponding digital output signals. The one or more digital output signals are compensated to compensate for the adjustment of the inputs of the DAC.

A current sensing system and delta sigma modulator architecture are discloses for sensing and digitizing a current input signal from a high impedance signal source with improve power efficiency. The delta sigma modulator integrates a signal condition stage within the delta sigma modulator feedback loop by utilizing a capacitive summation stage. For given gain, resolution, and bandwidth requirements, the delta sigma modulator architecture achieves reduced power consumption by advantageously reducing the number of nodes in the system that require a high dynamic range. Additionally, the delta sigma modulator has very high input impedance such that the input of the delta-sigma modulator can be connected directly to a high impedance signal source, without the need for a front-end pre-amplifier stage, or the like.

In one embodiment, an analog-to-digital converter includes: a sum circuit to receive an analog input signal and a feedback reference signal and generate a sum signal; a feedback circuit coupled to the sum circuit to provide the feedback reference signal to the sum circuit; a filter coupled to the sum circuit to receive the sum signal and generate a filtered signal; and a punctured quantizer coupled to the filter to receive the filtered signal and quantize the filtered signal to a digital output and to output the digital output and to provide the digital output to the feedback circuit.

Switching circuits controllable to force an input into a circuit and to sense a responsively produced output in multiple ways to produce different combinations of positive and negative polarities of a desired signal and of sources of offsets and 1/f noise. The switching circuits are controlled in a non-ordered time sequence of different combinations of positive and negative polarities of the sources of the offsets and 1/f noise that spreads their energy to a frequency range above the desired signal frequency band. The non-ordered time sequence leaves the polarity of the desired signal unchanged. Uncorrelated delta-sigma modulators may generate the control signal. A DSP processes a resulting spectrum of a digital domain version of the sensed output to measure residual offsets and 1/f noise and adds to an input present at the DSMs a signal equal in magnitude and opposite in sign to the measured residual offsets and 1/f noise.

An offset compensation circuit comprises an error signal generation block arranged for receiving an input phase and an output phase, and for generating an error signal indicative of an error between the input phase and the output phase. Means are provided for combining the error signal with an offset compensation signal, yielding an offset compensated signal. A loop filter is arranged for receiving the offset compensated signal and for outputting the output phase. An offset compensation block is arranged for receiving the output phase and for determining the offset compensation signal. The offset compensation signal comprises at least a contribution proportional to a periodic function of the output phase.

Methods adapted for digital-to-analog conversion compensation and systems are described. In a compensation method, inputs of a digital-to-analog converter (DAC) are adjusted to provide an even number inputs for the DAC. Further, one or more analog input signals are converted to generate one or more corresponding digital output signals. The one or more digital output signals are compensated to compensate for the adjustment of the inputs of the DAC.