Patent classifications
H03M3/406
AMPLIFIER CIRCUIT
A loop-filter comprising: a first-integrator, and one or more further-integrators. The first-integrator is an active-RC integrator, and comprises a first-integrator-input-terminal configured to receive: (i) an input-signal, and (ii) a feedback-signal; a first-integrator-first-output-terminal configured to provide a first-integrator-first-output-signal; and one or more first-integrator-further-output-terminals. Each of the one or more further-integrators is a Gm-C integrator, and they are connected in series between the first-integrator-first-output-terminal and a loop-filter-output-terminal. For a first further-integrator in the series, the further-integrator-input-terminal is configured to receive the first-integrator-first-output-signal. For any subsequent further-integrators in the series, the further-integrator-input-terminal is configured to receive: (i) the further-integrator-output-signal from the preceding further-integrator in the series; and (ii) one of the first-integrator-further-output-signals.
Analog-to-digital converter with bandpass noise transfer function
Methods and apparatus for providing bandpass analog to digital conversion (ADC) in RF receiver circuitry of a wireless-communication device. The bandpass ADC includes first noise-shaping successive approximation register (NS-SAR) circuitry arranged in a first path and second NS-SAR circuitry arranged in a second path parallel to the first path, wherein the first and second NS-SAR circuitries are configured to alternately sample an analog input voltage at a particular sampling rate and to output a digital voltage at the particular sampling rate.
ANALOG-TO-DIGITAL CONVERTER WITH BANDPASS NOISE TRANSFER FUNCTION
Methods and apparatus for providing bandpass analog to digital conversion (ADC) in RF receiver circuitry of a wireless-communication device. The bandpass ADC includes first noise-shaping successive approximation register (NS-SAR) circuitry arranged in a first path and second NS-SAR circuitry arranged in a second path parallel to the first path, wherein the first and second NS-SAR circuitries are configured to alternately sample an analog input voltage at a particular sampling rate and to output a digital voltage at the particular sampling rate.