H03M3/424

ANALOG-TO-DIGITAL CONVERTER
20220368341 · 2022-11-17 ·

An analog-to-digital converter includes a primary converter and a secondary converter. The primary converter executes conversion processing to convert an analog input signal to a first digital signal through delta-sigma modulation. The secondary converter outputs a second digital signal by converting amplified analog output of a quantization error in the primary converter to the second digital signal.

CLASS A AMPLIFIER WITH PUSH-PULL CHARACTERISTIC

An amplifier circuit comprises a first amplifier circuit stage including input devices connected to inputs of the amplifier circuit, a second amplifier circuit stage coupled to the first amplifier stage, a common mode extraction circuit configured to extract a DC common mode voltage of the first amplifier stage, and a bias circuit configured to bias one or more output devices of the second amplifier circuit stage using the DC common mode voltage.

Quantizer for sigma-delta modulator, sigma-delta modulator, and noise-shaped method

A quantizer for a sigma-delta modulator, a sigma-delta modulator, and a method of shaping noise are provided. The quantizer includes: an integrator configured to generate, in a K.sup.th sampling period, a quantization error signal for a K.sup.th period according to an internal signal, a quantization error signal for a (K−1).sup.th period, a filtered quantization error signal for the (K−1).sup.th period and a filtered quantization error signal for a (K−2).sup.th period; an integrating capacitor configured to store the quantization error signal for the K.sup.th period, to weight the internal signal in a (K+1).sup.th sampling period; a passive low-pass filter configured to acquire the quantization error signal for the K.sup.th period in a K.sup.th discharge period, and feed back the filtered quantization error signal to the integrator in a (K+1).sup.th sampling period and a (K+2).sup.th sampling period; and a comparator configured to quantize the quantization error signal for the K.sup.th period.

LOW POWER AND HIGH SPEED DATA WEIGHTED AVERAGING (DWA) TO BINARY CONVERTER CIRCUIT

A data weighted averaging (DWA) data word in a standard or normal form unary code format is first converted to a thermometer control word in an alternative or spatial form unary code format. The thermometer control word is then converted from the alternative or spatial form unary code format to output a corresponding binary word.

Thermometer coding for driving non-binary signals
11626886 · 2023-04-11 · ·

Methods, systems, and devices for thermometer coding for driving non-binary signals are described. A set of drivers may be used to drive a signal line, with each of the drivers calibrated to have different individual drive strengths. To drive a signal line to successive voltages in accordance with a non-binary modulation scheme, additional individual drivers of the set may be used. The different drive strengths of the individual drivers of the set may scale in non-linear fashion, which may offset non-linearities associated with the individual drivers as additional individual drivers of the set are activated.

DELTA-SIGMA MODULATION TYPE A/D CONVERTER
20230208435 · 2023-06-29 ·

A delta-sigma modulation type A/D converter includes: a capacitively coupled amplifier having a sampling capacitor, a feedback capacitor, and an amplifier; a correlated double sampling type first integrator as a first-stage integrator, which is connected to the capacitively coupled amplifier without a switch; a second integrator arranged after the first integrator; a quantizer arranged after the second integrator and quantizing an output of the second integrator; and an D/A converter that D/A-converts an output of the quantizer and feeds back to any one of the capacitively coupled amplifier, the first integrator, and the second integrator.

SPLIT PULSE WIDTH MODULATION TO REDUCE CROSSBAR ARRAY INTEGRATION TIME
20230198511 · 2023-06-22 ·

A computer-implemented method, according to one embodiment, includes: causing a multi-bit input to be split into two or more chunks, where each of the two or more chunks include at least one individual bit. Each of the two or more chunks are also converted into a respective pulse width modulated signal, and a partial result is generated in digital form for each of the respective pulse width modulated signals. Each of the partial results are scaled by a respective significance factor corresponding to each of the two or more chunks, and the scaled partial results are also accumulated.

Class A amplifier with push-pull characteristic

An amplifier circuit comprises a first amplifier circuit stage including input devices connected to inputs of the amplifier circuit, a second amplifier circuit stage coupled to the first amplifier stage, a common mode extraction circuit configured to extract a DC common mode voltage of the first amplifier stage, and a bias circuit configured to bias one or more output devices of the second amplifier circuit stage using the DC common mode voltage.

ANALOG-TO-DIGITAL CONVERTER WITH EMBEDDED NOISE-SHAPED TRUNCATION, EMBEDDED NOISE-SHAPED SEGMENTATION AND/OR EMBEDDED EXCESS LOOP DELAY COMPENSATION
20170353192 · 2017-12-07 ·

An exemplary quantizer includes a multi-bit analog-to-digital converter (ADC) and a first digital-to-analog converter (DAC) feedback circuit. The multi-bit ADC has an internal DAC associated with comparison of each sampled analog input of the multi-bit ADC. The multi-bit ADC converts a currently-sampled analog input into a first digital output. A first noise-shaped truncation output is derived from the first digital output. The first DAC feedback circuit transfers a first truncation residue associated with the first noise-shaped truncation output to the internal DAC. The transferred first truncation residue is reflected in comparison of a later-sampled analog input of the multi-bit ADC via the internal DAC.

Device for operating passive infrared sensors
09829382 · 2017-11-28 · ·

A system for measuring a sensor having two terminals includes first and second transistors with first and second control signal inputs connected to the sensor terminals. The system further includes a current divider including a reference current input, a current divider control input and first and second current outputs connected to the first and second transistors. First and second load circuits are connected to the first and second transistors at first and second differential output nodes. First and second integrator circuits are connected to the first and second differential output nodes. A comparator is driven by first and second differential output nodes. The comparator output controls a digital filter. A value of the a current divider control signal driving the current divider control input depends at least indirectly from the digital filter output.