A digitally-controlled oscillator (DCO) circuit includes a digital-to-analog converter (DAC) to generate a first current based on most significant bits of a multi-bit code received from a time-to-digital converter (TDC) of a digital phase-locked loop (PLL). The DCO circuit further includes a sigma-delta modulator (SDM) to modulate least significant bits of the multi-bit code into a set of digital bits based on a first frequency of a feedback clock of the DPLL. The set of digital bits is to cause the DAC to generate a second current. The DCO circuit further includes a ring oscillator coupled to the DAC, the ring oscillator to generate an alternating-current (AC) output signal having a second frequency corresponding to a combination of the first current and the second current.

In some embodiments, an analog-to-digital converter (ADC) architecture can be implemented to process a signal from a charge output sensor. The ADC architecture can include a summing node for receiving a sensor signal from the charge output sensor, and an output node implemented to provide a digital signal representative of the sensor signal. The ADC architecture can further include a charge amplifier implemented to receive an analog signal from the summing node as an input analog signal and generate an output analog signal with a gain, and an ADC circuit implemented to generate the digital signal based on the output analog signal from the charge amplifier. The ADC architecture can further include a feedback circuit implemented between the output node and the summing node.

An analog signal processor includes a sampling unit configured to (i) filter, in the frequency domain, a received time domain analog signal into a low-frequency end of a corresponding frequency spectrum, (ii) sample the filtered analog signal at a frequency substantially higher than the low-frequency end, and (iii) spread quantization noise over an expanded Nyquist zone of the corresponding frequency spectrum. The processor further includes a noise shaping unit configured to shape the spread quantization noise out of the low-frequency end of the corresponding frequency spectrum such that the filtered analog signal and the shaped quantization noise are substantially separated in the frequency domain, and a quantization unit configured to apply delta-sigma modulation to the filtered analog signal using at least one quantization bit, and output a digitized bit stream that substantially follows the amplitude of the received time domain analog signal.

An electronic amplification-interface circuit includes a differential-current reading circuit having a first input terminal and a second input terminal. The differential-current reading circuit includes a continuous-time sigma-delta conversion circuit formed by an integrator-and-adder module generating an output signal that is coupled to an input of a multilevel-quantizer circuit configured to output a multilevel quantized signal. The integrator-and-adder module includes a differential current-integrator circuit configured to output a voltage proportional to an integral of a difference between currents received at the first and second input terminals. A digital-to-analog converter, driven by a respective reference current, receives and converts the multilevel quantized signal into a differential analog feedback signal. The integrator-and-adder module adds the differential analog feedback signal to the differential signal formed at the first and second input terminals.

An analog signal processor includes a sampling unit configured to (i) filter, in the frequency domain, a received time domain analog signal into a low-frequency end of a corresponding frequency spectrum, (ii) sample the filtered analog signal at a frequency substantially higher than the low-frequency end, and (iii) spread quantization noise over an expanded Nyquist zone of the corresponding frequency spectrum. The processor further includes a noise shaping unit configured to shape the spread quantization noise out of the low-frequency end of the corresponding frequency spectrum such that the filtered analog signal and the shaped quantization noise are substantially separated in the frequency domain, and a quantization unit configured to apply delta-sigma modulation to the filtered analog signal using at least one quantization bit, and output a digitized bit stream that substantially follows the amplitude of the received time domain analog signal.

Reference scaling, op amp balancing and chopper stabilization techniques for delta-sigma modulators of analog-to-digital converters are provided. For reference scaling, unit elements in a feedback digital-to-analog (DAC) converter are driven by a reference voltage or disconnected from active circuitry to realize three DAC levels. While disconnected, the unit elements deliver no charge to the device which results in power saving and a reduction in thermal noise. Op amp balancing involves down-sampling the quantizer output followed by up-sampling on the feedback path and filtering to hold a DAC value of the signal for a duration of a sampling period to generate the feedback signal. Chopper stabilization is performed by chopping an operational transconductance amplifier of the integrator at a chopping frequency equal to the sampling frequency.

An electronic amplification-interface circuit includes a differential-current reading circuit having a first input terminal and a second input terminal. The differential-current reading circuit includes a continuous-time sigma-delta conversion circuit formed by an integrator-and-adder module generating an output signal that is coupled to an input of a multilevel-quantizer circuit configured to output a multilevel quantized signal. The integrator-and-adder module includes a differential current-integrator circuit configured to output a voltage proportional to an integral of a difference between currents received at the first and second input terminals. A digital-to-analog converter, driven by a respective reference current, receives and converts the multilevel quantized signal into a differential analog feedback signal. The integrator-and-adder module adds the differential analog feedback signal to the differential signal formed at the first and second input terminals.

The present disclosure relates generally to techniques for linearizing a digital-to-analog converter (DAC) in a continuous-time sigma-delta ADC. A sigma-delta ADC may be configured with a multibit quantizer for various applications. These applications may require wide-bandwidth high-resolution high-linearity power-efficient ADCs. In some embodiments, a mismatch of a multibit DAC might result in a bottleneck for achieving high linearity performance. Some linearization techniques may achieve high linearity performance. However, for a high-speed sigma-delta ADC, the DAC is configured to be part of a feedback loop. Existing linearization techniques often increase the delay in the feedback loop, which is not desired. Various aspects of the present disclosure provide improvement to linearization techniques by changing the references of the multibit quantizer. As a result, this reduces delay in the feedback loop of the sigma-delta modulator, which is beneficial for high-speed sigma-delta ADCs.

A sigma delta modulator device includes a sampling circuit, a digital to analog converter circuit, an integrator circuit, and an analog to digital converter circuit. The sampling circuit is configured to sample an input signal, in order to generate a first signal. The digital to analog converter circuit is configured to convert a first digital signal to be a combination of a first reference voltage and a common mode voltage, in order to generate a second signal, in which the first reference voltage is one of a positive reference voltage and a negative reference voltage. The integrator circuit is configured to perform integration according to the first signal and the second signal, in order to generate a third signal. The analog to digital converter circuit is configured to quantize the third signal to generate an output signal, and to generate the first digital signal according to the output signal.

The present disclosure relates generally to techniques for linearizing a digital-to-analog converter (DAC) in a continuous-time sigma-delta ADC. A sigma-delta ADC may be configured with a multibit quantizer for various applications. These applications may require wide-bandwidth high-resolution high-linearity power-efficient ADCs. In some embodiments, a mismatch of a multibit DAC might result in a bottleneck for achieving high linearity performance. Some linearization techniques may achieve high linearity performance. However, for a high-speed sigma-delta ADC, the DAC is configured to be part of a feedback loop. Existing linearization techniques often increase the delay in the feedback loop, which is not desired. Various aspects of the present disclosure provide improvement to linearization techniques by changing the references of the multibit quantizer. As a result, this reduces delay in the feedback loop of the sigma-delta modulator, which is beneficial for high-speed sigma-delta ADCs.