The present invention relates to a method for adjusting the resonance frequency of a loop filter in a delta-sigma modulator, e.g. in an angular rate sensor, to a predetermined frequency value, wherein the sigma-delta modulator comprises an input terminal, which is connected to the loop filter, a quantizer, which is connected to an output of the loop filter, and a feedback branch, which couples an output of the quantizer back to the input terminal. The method comprises the following steps: Optional rough adjustment of the resonance frequency of the filter by means of the regulating variable of a second oscillator, input of a filter input signal of the loop filter into a frequency adjustment circuit, determination of a noise spectrum of the filter input signal in a first frequency band and a second frequency band, wherein the first frequency band and the second frequency band are arranged symmetrically around the predetermined frequency, comparison of the noise spectra and creation of an adjustment signal that leads to a frequency adjustment when the noise spectra deviate from one another, and feedback of the adjustment signal of the frequency adjustment circuit to a control input of the loop filter for setting the filter frequency in response to the comparative result.

Systems and method for improving stability and performance in class-D modulators. In particular, a multi-cycle feedback network is positioned around a quantizer of a digital class-D amplifier. The multi-cycle feedback network allows the main class-D feedback loop to have multiple clock cycles of delay.

Instability of an internal state in a current-input-type delta-sigma modulator is reduced in a case where input changes sharply. A signal current is input to a first integration node. A difference current between a fixed current and the signal current is input to a second integration node. A voltage-to-current converter that converts a difference voltage between the voltage of the first integration node and a first reference voltage into a current and outputs it is connected between the first integration node and the second integration node. The voltage of the second integration node is compared with a second reference voltage, and a 1-bit digital signal is output. Current is draws from the first integration node or the second integration node according to the 1-bit digital signal. A short-circuit switch is provided between the first integration node and the second integration node for short-circuiting them.

An analog to digital converter (ADC) senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. The digital output signal provided to the N-bit DAC is an inverse function of the load current. The ADC is operative to sense very low currents (e.g., currents as low as is of pico-amps) and consume very little power (e.g., less than 2 μW).

A temperature sensor is disclosed. In one aspect, the temperature sensor provides a digital output having a precise degree/code step. For example, each step in the digital output code may correspond to one degree Celsius. In one aspect, a temperature sensor comprises a precision band-gap circuit and a sigma delta modulator (SDM) analog-to-digital convertor (ADC). A bandgap voltage and a PTAT voltage may be provided from the band-gap circuit as an input to the SDM ADC. The SDM ADC may produce an output based on the difference between the PTAT voltage and the bandgap voltage. The temperature sensor may also have logic that outputs a temperature code based on the output of the SDM ADC.

A digital temperature sensor circuit is disclosed. The digital temperature sensor circuit includes a proportional to the absolute temperature (PTAT) current source, generating a PTAT current proportional to absolute temperature; a sigma-delta modulation module, including an integrator, an analog-to-digital conversion unit, and a feedback digital-to-analog conversion unit; the integrator converts the PTAT current into temperature voltage; the analog-to-digital conversion unit compares the temperature voltage with a band gap reference voltage to generate a digital modulation signal with a duty ratio proportional to the temperature; the feedback digital-to-analog conversion unit adjusts the voltage input by the analog-to-digital conversion unit and controls the charging and discharging speed of the integrator; a digital filter, quantizing the digital modulation signal into a digital signal, and outputting the digital signal.

Systems and methods include a circuit having a plurality of integrator circuits arranged in series and configured to receive an input signal at a first of the plurality of integrators and generate an output signal at a last of the plurality of integrators, a filter arranged to receive a feedback signal comprising the output signal and generate a filtered feedback signal, which is applied to the input signal before input to the first of the plurality of integrators, and a feedback signal path configured to receive the feedback signal and apply the feedback signal to an input of a second of the plurality of integrators. The circuit may include a class-D amplifier and/or a delta-sigma modulator. The input signal may include an analog audio signal that is amplifier to drive an audio speaker.

A time constant calibration circuit and method. The circuit comprises a resistor, a capacitor, an amplifier, a first switch and a second switch. The resistance of the resistor and/or the capacitance of the capacitor is variable. A first terminal of the resistor, a first terminal of the capacitor and a first input of the amplifier are coupled to a common node, which is coupleable to a reference current source. A second input of the amplifier is coupleable to a reference voltage. An output of the amplifier is coupled to a second terminal of the resistor and a second terminal of the capacitor. The circuit can perform a calibration process comprising one or more calibration cycles in which the switches route a reference current through the resistor in a first phase and through the capacitor in a second phase. The resistance and/or the capacitance is adjusted between calibration cycles.

A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.

Provided is an AD converter, including: an analog signal input circuit, configured to be input with an analog input signal, and output a first analog output signal based on the analog input signal and a second analog output signal based on the analog input signal at different timing; an integral circuit, configured to integrate the first analog output signal and the second analog output signal and output the first integral signal and the second integral signal; a predictive circuit, configured to predict an integral signal output after the output by the integral circuit based on the first integral signal and the second integral signal output by the integral circuit, and output a predictive integral signal; and a quantization circuit, configured to generate a digital signal with the predictive integral signal quantized.