A digital lock-in controller for Resonant-type converters with one or more sub-circuits having resonant tanks and one or more flying capacitors connected across the resonant tanks, which comprises an auto-tuner that receives as input Zero-Current Detect (ZCD) signals and implements a tuning algorithm by performing arithmetic operations that ensure Zero-Current Switching (ZCS) operation for all resonant tanks in the converter; a digital hybrid High-Resolution (HR) sequencer that receives as input the switching times commands and generates a pulse-width-modulated signal that is fed into the gates of the converter's switching transistors; a sampling block with time resolution of a single delay-element, for accurately reading of the ZCD sensor's outputs; a governor module for performing all synchronization actions and dictating the operation mode of the controller, based on auxiliary configurations.

A photoelectric converter comprising a pixel unit and a processor configured to process a pixel signal output from the pixel unit is provided. The processor comprises a ΔΣ AD converter configured to convert the pixel signal into a digital signal. The ΔΣ AD converter comprises a subtracter to which the pixel signal and a subtraction signal are input, an integrator configured to receive an output from the subtracter, a comparator configured to compare an output from the integrator with a predetermined voltage, a decimation filter configured to generate the digital signal based on an output from the comparator, a delay unit configured to delay an output from the comparator, a buffer configured to buffer an output from the delay unit, and a DA converter configured to convert an output from the buffer into an analog signal to generate the subtraction signal.

A photoelectric conversion device comprising a pixel unit in which a plurality of pixels each comprising a photoelectric conversion element are arranged in a matrix, and a plurality of delta-sigma AD converters each configured to convert a signal output from the pixel unit into a digital signal, is provided. The plurality of delta-sigma AD converters are divided into at least two groups having different timings of starting AD conversion from each other when converting, into digital signals, signals output from the pixels selected out of the plurality of pixels via a common pixel control line.

A photoelectric conversion device includes a light receiving circuit configured to convert light into an electrical signal, a first hold circuit configured to hold a data signal which represents the electrical signal, a second hold circuit configured to hold a noise signal read out from the light receiving circuit in a reset state, a first resistive element to which a voltage corresponding to a difference between the data signal held by the first hold circuit and the noise signal held by the second hold circuit is applied, an A/D converter configured to convert an analog current flowing in the first resistive element into digital data, a second resistive element, and a temperature detection circuit configured to generate, based on a current flowing in the second resistive element, an analog output corresponding to an internal temperature of the photoelectric conversion device.

A N-bit continuous-time sigma-delta modulator, SDM, (800) includes an input configured to receive an input analog signal (302); a first summing junction (304) configured to subtract a feedback analog signal (303) from the input analog signal (302); a loop filter (306) configured to filter an output signal from the first summing junction (304): an N-bit analog-to-digital converter, ADC, comprising at least one 1-bit ADC configured to convert the filtered analog output signal (309) to a digital output signal (314) where each 1-bit ADC comprises at least one pair of comparator latches (336, 356); and a feedback path (316) for routing the digital output signal to the first summing junction (304). The feedback path (316) includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal (314) to an analog form. The ADC comprises or is operably coupled to, a calibration circuit (650, 840) coupled to an input and an output of the at least one pair of comparator latches (336, 356) and configured to apply respective calibration signals to individual comparator latches of the at least one pair of comparator latches (336, 356) in a time-Interleaved manner, and calibrate a comparator error of the comparator latches in response to a latched output of the respective calibration signals.

A system includes: a first temperature sensor configured to measure a first temperature of exhaust at a first location of an exhaust system of a vehicle; a second temperature sensor configured to measure a second temperature of exhaust at a second location of the exhaust system of the vehicle; a first analog to digital (A/D) converter configured to receive a first analog signal from the first temperature sensor, to sample the first analog signal to produce first samples, and to generate first digital values corresponding to the first temperature based on the first samples, respectively; and a second A/D converter a configured to receive a second analog signal from the second temperature sensor, to sample the second analog signal to produce second samples, and to generate second digital values corresponding to the second temperature based on the second samples, respectively.

Aspects of the technology described herein relate to built-in self-testing (BIST) of circuitry (e.g., a pulser or receive circuitry) and/or transducers in an ultrasound device. A BIST circuit may include a transconductance amplifier coupled between a pulser and receive circuitry, a capacitor network coupled between a pulser and receive circuitry, and/or a current source couplable to the input terminal of receive circuitry to which a transducer is also couplable. The collapse voltages of transducers may be characterized using BIST circuitry, and a bias voltage may be applied to the membranes of the transducers based at least in part on their collapse voltages. The capacitances of transducers may also be measured using BIST circuitry and a notification may be generated based on the sets of measurements.

Aspects of the technology described herein relate to built-in self-testing (BIST) of circuitry (e.g., a pulser or receive circuitry) and/or transducers in an ultrasound device. A BIST circuit may include a transconductance amplifier coupled between a pulser and receive circuitry, a capacitor network coupled between a pulser and receive circuitry, and/or a current source couplable to the input terminal of receive circuitry to which a transducer is also couplable. The collapse voltages of transducers may be characterized using BIST circuitry, and a bias voltage may be applied to the membranes of the transducers based at least in part on their collapse voltages. The capacitances of transducers may also be measured using BIST circuitry and a notification may be generated based on the sets of measurements.

An analog to digital converter (ADC) senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. The digital output signal provided to the N-bit DAC is an inverse function of the load current. The ADC is operative to sense very low currents (e.g., currents as low as is of pico-amps) and consume very little power (e.g., less than 2 μW).

A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.