This disclosure is directed to, among other things, techniques to decouple the number of bits in a quantizer from the number of bits in the feedback digital-to-analog converter (DAC). A delta-sigma analog-to-digital converter circuit can include a first quantizer to generate an output having a first number of bits and then emulate a second quantizer, such as by using a bit truncation technique, to generate an output having a second number of bits. The feedback DAC can be coupled to receive the second number of bits, where the output of the feedback digital-to-analog converter circuit has the second number of bits. These techniques can reduce the area of the feedback DAC, e.g., 4 or 5 bits, and the techniques can achieve a higher maximum stable amplitude (MSA) because it is effectively a second order loop.

A calibration circuit, including: a signal generator circuit configured to generate a modulated analog input signal, which is based on a digital input word that is modulated; an Analog-to-Digital Converter (ADC) configured to convert an analog reference signal to a digital calibration word, wherein the analog reference signal is a low-pass-filtered version of the analog input signal generated by the signal generator circuit; and a feedback circuit configured to output the digital input word by adjusting the digital calibration word depending on a digital feedback signal, which is based on a modulated version of the analog reference signal, wherein the signal generator circuit, the ADC, and the feedback circuit are provided on a same chip.

An amplifier circuit comprises a first amplifier circuit stage including input devices connected to inputs of the amplifier circuit, a second amplifier circuit stage coupled to the first amplifier stage, a common mode extraction circuit configured to extract a DC common mode voltage of the first amplifier stage, and a bias circuit configured to bias one or more output devices of the second amplifier circuit stage using the DC common mode voltage.

An apparatus comprises a sigma-delta analog-to-digital converter (ADC) circuit configured to convert an analog input signal to a digital value. The sigma-delta ADC circuit includes a loop filter circuit including at least one loop filter amplifier, a flash ADC circuit including multiple comparators, and a bias control circuit configured to change a biasing of the at least one loop filter amplifier according to outputs of the multiple comparators of the flash ADC circuit.

A sigma delta analog-to-digital converter (ADC) circuit comprises a capacitive gain amplifier circuit having a first input to receive an input voltage and a second input; a loop filter circuit connected to an output of the capacitive gain amplifier circuit; a sub-ADC circuit including an output and an input connected to an output of the loop filter circuit; and a digital-to-analog (DAC) circuit including a DAC input connected to the output of the sub-ADC circuit, and a DAC output connected to the second input of the capacitive gain amplifier.

An apparatus comprises a delta-sigma analog-to-digital converter (ADC) and baseband processing circuitry. The delta-sigma ADC includes a plurality of integrator stages connected in series, including a first integrator stage operatively coupled to an input of the delta-sigma ADC; a main quantizer circuit including a main ADC circuit and a main digital-to-analog converter (DAC) circuit, wherein an input to the main ADC circuit is operatively coupled to the plurality of integrator stages; and a first feedback circuit path operatively coupled from an output of the first integrator stage to the input of the delta-sigma ADC, wherein the first feedback circuit path is configured to subtract an output voltage of the first integrator stage from the input of the delta-sigma ADC. The baseband circuitry is configured to activate the first feedback circuit path when detecting that the input voltage increases to cause distortion in the delta-sigma ADC.

Systems and method for improving stability and performance in class-D modulators. In particular, a multi-cycle feedback network is positioned around a quantizer of a digital class-D amplifier. The multi-cycle feedback network allows the main class-D feedback loop to have multiple clock cycles of delay.

In accordance with an embodiment, a method of operating an oversampled data converter having a switched-capacitor (SC) integrator includes operating the oversampled data converter in a gain calibration mode; applying a first voltage to a feedback port of the SC integrator to form a feedback voltage, and during a first clock phase the method further includes applying the first voltage to a first series capacitor via the input port when an output of the oversampled data converter is in a first state; applying a bypass voltage to the first series capacitor when the output of the oversampled data converter is an a second state and applying the first voltage to a second series capacitor via the feedback port with a polarity based on the output of the oversampled data converter, and during a second clock phase the method includes integrating charges of the first series capacitor and the second series capacitor.

A delta-sigma Analog-to-Digital Converter (ADC) (IC) which includes an input feed-forward path extending from an input to the ADC to a feed-forward summing circuit disposed between a loop filter and quantizer of the ADC, and a filter disposed in the feed-forward path as an apparatus for improving distortion performance in the delta-sigma ADC. The filter may be a low pass filter, for example, a Resistor-Capacitor (RC) circuit. The filter may have a cut-off frequency outside the ADC's passband. The filtering provided may be continuous-time filtering, even if the delta-sigma ADC is a discrete-time delta-sigma ADC.

The present disclosure relates generally to digital microphone and other sensor assemblies including a transducer and a delta-sigma analog-to-digital converter (ADC) with digital-to-analog converter (DAC) element mismatch shaping and more particularly to sensor assemblies and electrical circuits therefor including a dynamic element matching (DELM) entity configured to select DAC elements based on data weighted averaging (DWA) and a randomized non-negative shift.