A communication unit (300, 400, 500) is described that includes at least one antenna (302, 402, 502); a plurality of radio frequency (RF) circuits (304, 310, 404, 410) respectively coupled to at least one antenna (302, 402, 502); at least one sigma-delta modulator (316, 416, 616, 816) comprising a number of stages, each stage comprising at least one signal-feedforward coefficient (603, 604, 605), a filter and a feedback gain element, the at least one sigma-delta modulator (316, 416, 616, 816) coupled to the plurality of RF circuits (304, 310, 404, 410) and configured to perform sigma-delta modulation; and a controller (340, 440, 640, 840) operably coupled to the at least one sigma-delta modulator (316, 416, 616, 816). The at least one sigma-delta modulator (316, 416, 616, 816) comprises an input (315, 415, 602, 801, 802, 902) configured to receive multiple multi-phase input signals and the controller (340, 440, 640, 840) is configured to adjust the at least one signal-feedforward coefficient (603, 604, 605) of the at least one sigma-delta modulator (316, 416, 616, 816) when combining the multiple multi-phase input signals.

A class-D amplifier includes measurement of speaker current via the low-side drive transistors of the amplifier. In one embodiment, a class-D amplifier includes two high-side transistors, two low-side transistors, a first sense resistor, a second sense resistor, and a sigma delta analog to digital converter ( ADC). The two high-side transistors and two low-side transistors are connected as a bridge to drive a bridge tied speaker. The first sense resistor is connected between a first of the low-side transistors and a low-side reference voltage. The second sense resistor is connected between a second of the low-side transistors and the low-side reference voltage. The ADC is coupled to the bridge to measure voltage across the first sense resistor and the second sense resistor.

Various embodiments relate to delta-sigma loop filters with input feedforward. A delta-sigma loop filter may include a first integrator and a quantizer having an input coupled to an output of the first integrator. The delta-sigma loop filter may further include a first summing node having an output coupled to an input of the first integrator. Further, the delta-sigma loop filter may include a feedforward path from an input of the delta-sigma loop filter to a first input of the first summing node. The delta-sigma loop filter may also include a first feedback path from an output of the quantizer to a second input of the first summing node.

Various embodiments relate to an analog-to-digital converter (ADC). The ADC may include a first channel including a first delta-sigma loop filter and a second channel including a second delta-sigma loop filter. Each of the first delta-sigma loop filter and the second delta-sigma loop filter may include a first integrator and a quantizer having an input coupled to an output of the first integrator. Each of the first delta-sigma loop filter and the second delta-sigma loop filter may also include a first summing node having an output coupled to an input of the first integrator, and a feedforward path from an input of the delta-signal loop filter to a first input of the first summing node. Further, each of the first delta-sigma loop filter and the second delta-sigma loop filter may include a first feedback path from an output of the quantizer to a second input of the first summing node.

Techniques for a configurable analog-to-digital converter filter to ameliorate transfer function peaking or frequency response issues are provided. In an example, a front-end circuit of a processing circuit can include a resistor-capacitor filter including at least two capacitors and a switch circuit. The resistor-capacitor filter can couple an input analog signal to the processing circuit. The switch circuit can couple to a first capacitor of the at least two capacitors, and can selectively place a terminal of the first capacitor at a selected one of a plurality of distinct nodes of the resistor-capacitor filter to configure the circuit to address the peaking or frequency response issue.

A modulator includes a first integrator which has first and second capacitors and integrates an analog input signal and a feedback analog signal, a second integrator which has third and fourth capacitors and integrates an output signal of the first integrator, a differential amplifier which has input and output terminals switched and connected via a switch circuit to either the first and second capacitors or the third and fourth capacitors, a chopper switch which switches the polarity of the input terminal and the polarity of the output terminal, to both of which the first capacitor and the second capacitor are connected, a quantizer which compares an added signal and a reference signal to output a digital value, and a digital/analog converter which outputs the feedback analog signal corresponding to the digital value.

An analog-to-digital conversion method and an A/D conversion device for a temperature sensor are provided. An analog front-end circuit generates an A/D converter input signal positively correlated to a temperature and an A/D converter reference voltage signal negatively correlated to the temperature, and an operation is performed on a ratio of amplitudes of the generated signals to obtain a quantized output value. Since the amplitude of the A/D converter input signal is less than that of the A/D converter reference voltage signal, measurements on other signals is compatible with the measurement on the temperature in a multi-sensor system. A digitized output value is calculated by a digital-assisted readout method to generate a linear output relating to a temperature, thereby improving the accuracy of temperature measurement and reducing complexity of analog circuit design.

A quantizer includes: a quantizer capacitor having a first end and a second end; an input calculator that receives input voltages, sums the input voltages, and outputs the summed result to the first end of the quantizer capacitor; a scaler that receives reference voltages and a scale code, generates a scale voltage from the reference voltages depending on the scale code, and outputs the scale voltage to the second end of the quantizer capacitor; and a latch that stores an output voltage of the first end of the quantizer capacitor.

A semiconductor device includes; a loop filter that receives a differential analog signal and generates a residue signal indicating an error between an analog input signal and an feedback signal, a first ADC that receives the residue signal and generates a first digital representation, a second ADC that receives the analog input signal and generates a second digital representation corresponding to the analog input signal, and a digital to analog converter (DAC) that receives a sum of the first digital representation and the second digital representation and generates the analog feedback signal. At least the first ADC is a multi-bit Successive Approximation Register ADC.

A feedback control system configured to drive a load is disclosed. The feedback control system includes an up-sampling circuit, configured to perform an un-sampling operation on a source signal and produce an up-sampled signal with an up-sampling frequency according to the up-sampled signal and a feedback signal from the load; a delta circuit, coupled to the up-sampling circuit and configured to produce a delta signal; a sigma circuit, configured to produce a density modulation signal according to the delta signal; and a driving device, configured to drive the load according to the density modulation signal with the up-sampling frequency.