Radio-frequency (RF) receivers having bandpass sigma-delta analog sigma analog-to-digital converters (ADC) designed to digitize signals in the RF domain are described. Such bandpass ADCs utilize one or more of the following techniques to enhance noise immunity and reduce power consumption: generation of in-phase (I) and quadrature (Q) paths in the digital domain, n.sup.th order resonant bandpass filtering with n>1, and signal sub-sampling in an i.sup.th Nyquist zone with i>1. Compared to RF receivers in which the I and Q paths are generated in the analog domain, these RF receivers exhibit higher IRRs because they are not susceptible to in-phase/quadrature (IQ) mismatch. Using n.sup.th order resonant bandpass filtering with n>1 attenuates unwanted image tones. The bandpass ADC-based RF receivers described herein exhibit enhanced immunity to noise, achieving for example image rejection ratios (IRR) in excess of 95 dB.

A delta-sigma modulator generates a bit stream signal from an analog signal by operating according to a modulation period including a sampling period and a filtering period and includes a digital-to-analog converter (DAC) configured to generate a charge signal according to one of a first reference voltage and a second reference voltage according to the bit stream signal during the sampling period and to output a signal generated according to the charge signal and the other of the first reference voltage and the second reference voltage; a loop filter configured to charge a sampling signal corresponding to the analog signal during the sampling period and to filter an output from the DAC and a signal generated according to the sampling signal during the filtering period; and a quantizer configured to generate the bit stream signal according to an output from the loop filter in the modulation period.

An input device includes a clocked comparator configured to actively drive a capacitive sensor electrode at a signal input of the clocked comparator with a first periodic reference voltage, and provide a digital representation of a sensing current resulting from driving the capacitive sensor electrode with the first periodic reference signal. The clocked comparator produces the digital representation of the sensing current based on a comparison of the signal input of the clocked generator with the first periodic reference signal. A feedback path provides negative feedback of the digital representation of the sensing current to the signal input of the clocked comparator. The input device further includes a demodulator configured to demodulate the digital representation of the sensing current using the first periodic reference signal to obtain a first digital measurement.

A digital microphone includes built-in self-test features. The features may include capability to apply different bias voltages to a MEMS capacitor sensor of the digital microphone, simulating application of different sound pressures to the digital microphone. The features may also include a digital oscillator, for applying a test signal to an analog front end of the microphone.

Various embodiments relate to delta-sigma loop filters with input feedforward. A delta-sigma loop filter may include a first integrator and a quantizer having an input coupled to an output of the first integrator. The delta-sigma loop filter may further include a first summing node having an output coupled to an input of the first integrator. Further, the delta-sigma loop filter may include a feedforward path from an input of the delta-sigma loop filter to a first input of the first summing node. The delta-sigma loop filter may also include a first feedback path from an output of the quantizer to a second input of the first summing node.

A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.

A method includes using a first feedback loop to compensate for a first excess loop delay (ELD) associated with a first quantizer and a first DAC of the first feedback loop. The first quantizer provides a first quantizer output to a second feedback loop. A second feedback loop compensates for a second ELD associated a second quantizer and a second DAC of the second feedback loop. The second quantizer reduces a metastability error associated with the first quantizer output.

Various embodiments relate to an analog-to-digital converter (ADC). The ADC may include a first channel including a first delta-sigma loop filter and a second channel including a second delta-sigma loop filter. Each of the first delta-sigma loop filter and the second delta-sigma loop filter may include a first integrator and a quantizer having an input coupled to an output of the first integrator. Each of the first delta-sigma loop filter and the second delta-sigma loop filter may also include a first summing node having an output coupled to an input of the first integrator, and a feedforward path from an input of the delta sigma loop filter to a first input of the first summing node. Further, each of the first delta-sigma loop filter and the second delta-sigma loop filter may include a first feedback path from an output of the quantizer to a second input of the first summing node.

Described is an apparatus which comprises: a first integrator to receive an input signal and to generate a first output; a second integrator to receive the first output or a version of the first output and to generate a second output; and an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit to detect an overload condition in the second output.

Included are a loop filter, a quantization circuit section, and a current steering digital-analog conversion section. The quantization circuit section converts a loop filter output into a digital value. The current steering digital-analog conversion section is provided in a feedback loop that feeds back the output of the quantization circuit section to the loop filter. Then, each of the analog-digital converters includes a first input signal current path, a second input signal current path, a first feedback current path, and a second feedback current path. The first input signal current path feeds a first input signal current to an input end of a first stage integrator of the loop filter. The second input signal current path feeds a second input signal current, a current opposite in sign to the first input signal current, to an input end of a second stage integrator of the loop filter. The first feedback current path connects one feedback output end of the current steering digital-analog conversion section to the input end of the first stage integrator of the loop filter. The second feedback current path connects other feedback output end of the current steering digital-analog conversion section to the input end of the second stage integrator of the loop filter.