A modulator circuit includes a plurality of signal processing branches, each branch having a modulator for performing a delta-sigma modulation of a respective data stream portion in order to generate a modulated signal. The modulator circuit receives an input data stream having a carrier frequency; splits the input data stream into a plurality of data stream portions. Delta-sigma modulation is performed in each branch on a respective data stream portion. The respective modulated signals from each branch are combined to form an output signal for outputting at the carrier frequency.

An electric control device includes a first delta sigma modulator having a clock input connection, a second delta sigma modulator having a clock input connection, and an evaluation unit. The evaluation unit includes a first clock output connection which is connected to the clock input connection of the first delta sigma modulator by a first electrical cable, and a second clock output connection which is connected to the clock input connection of the second delta sigma modulator by a second electrical cable. The evaluation unit is designed to generate a clock signal (CLK1) at the first clock output connection (7) in phase opposition to a clock signal (CLK2) at the second clock output connection (9).

A modulator of an analog to digital converter includes a quantizer component configured to generate a digital signal based on a clock input operating at a sample rate. The modulator further includes a first digital to analog converter (DAC) configured to generate first DAC output at half the sample rate. The modulator further includes a second DAC configured to generate second DAC output at half the sample rate, where the first DAC and the second DAC are updated at alternate cycles of the clock input.

A modulator of an analog to digital converter includes a quantizer component configured to generate a digital signal based on a clock input operating at a sample rate. The modulator further includes a first digital to analog converter (DAC) configured to generate first DAC output at half the sample rate. The modulator further includes a second DAC configured to generate second DAC output at half the sample rate, where the first DAC and the second DAC are updated at alternate cycles of the clock input.

A delta-sigma modulator comprising: a first loop filter for filtering a first signal to a second signal, a second loop filter for filtering a third signal, a comparator, a register coupled to the comparator, a first capacitor bank and a second capacitor bank parallelly coupled between the second loop filter and the comparator, a first path causing a delayed signal to be linearly combined with an input signal to form the first signal, and a second path causing the delayed signal to be linearly combined with the second signal to form the third signal, wherein the delayed signal may be formed by delaying an output signal of the register.

A delta-sigma modulator comprising: a first loop filter for filtering a first signal to a second signal, a second loop filter for filtering a third signal, a comparator, a register coupled to the comparator, a first capacitor bank and a second capacitor bank parallelly coupled between the second loop filter and the comparator, a first path causing a delayed signal to be linearly combined with an input signal to form the first signal, and a second path causing the delayed signal to be linearly combined with the second signal to form the third signal, wherein the delayed signal may be formed by delaying an output signal of the register.

The present invention relates to an incremental analog to digital converter incorporating noise shaping and residual error quantization. In one embodiment, a circuit includes an incremental analog to digital converter, comprising a loop filter that filters an analog input signal in response to receiving a reset signal, resulting in a filtered analog input signal, and a successive approximation register (SAR) quantizer, coupled with the filtered analog input signal, that converts the filtered analog input signal to an intermediate digitized output of a first resolution based on a reference voltage, wherein the SAR quantizer comprises a feedback loop that shapes quantization noise generated by the SAR quantizer as a result of converting the filtered analog input signal; and a digital filter, coupled with the intermediate digitized output, that generates a digitized output signal of a second resolution, greater than the first resolution, by digitally filtering the intermediate digitized output.

The present invention provides a continuous-time delta-sigma modulator comprising two ADCs. One of the ADC is configured to generate MSBs of an output signal of the continuous-time delta-sigma modulator, and the other ADC is configured to generate LSBs of the output signal. In addition, the two ADCs sample an output of a loop filter at different times, but the MSBs and LSBs are feedback to the loop filter simultaneously.

A Delta-Sigma modulator architecture is disclosed that uses interleaving and dynamic matching algorithms to address the needs of multi-mode, multi-band high bandwidth transmitters. The proposed architecture also supports a novel software defined transmitter architecture based on an interleaved Delta-Sigma modulator to generate RF signals. The proposed architecture leverages interleaving concepts to relax subcomponent clock rates without changing the effective oversampling ratio, thus, making it easier to reach aggressive dynamic range goals across wider bandwidths at higher frequencies. The DEM algorithm helps to randomize mismatch errors across all interleaved paths and improves substantially the signal-to-noise ratio. Additionally, a tunable bandpass filter can be added to reject out-of-band emissions.

A Delta-Sigma modulator architecture is disclosed that uses interleaving and dynamic matching algorithms to address the needs of multi-mode, multi-band high bandwidth transmitters. The proposed architecture also supports a novel software defined transmitter architecture based on an interleaved Delta-Sigma modulator to generate RF signals. The proposed architecture leverages interleaving concepts to relax subcomponent clock rates without changing the effective oversampling ratio, thus, making it easier to reach aggressive dynamic range goals across wider bandwidths at higher frequencies. The DEM algorithm helps to randomize mismatch errors across all interleaved paths and improves substantially the signal-to-noise ratio. Additionally, a tunable bandpass filter can be added to reject out-of-band emissions.