Provided are, among other things, systems, apparatuses, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. One such apparatus includes an input line for accepting an input signal that is continuous in time and continuously variable, multiple processing branches coupled to the input line, and an adder coupled to outputs of the processing branches. Each of the processing branches includes a continuous-time quantization-noise-shaping circuit, a sampling/quantization circuit coupled to an output of the continuous-time quantization-noise-shaping circuit, a digital bandpass filter coupled to an output of the sampling/quantization circuit, and a line coupling an output of the digital-to-analog converter circuit back into the continuous-time quantization-noise-shaping circuit. A center frequency of the digital bandpass filter in each the processing branch corresponds to a minimum in a quantization noise transfer function for the continuous-time quantization-noise-shaping circuit in the same processing branch.

Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

A multi-rate cascaded continuous-time analog-to-digital converter has a plurality of sigma-delta modulator stages and includes first and second continuous-time sigma-delta modulators, and a summation element. The first continuous-time sigma-delta modulator operates at a first sampling rate. The second continuous-time sigma-delta modulator operates at a second sampling rate higher than the first sampling rate. The second continuous-time sigma-delta modulator has a continuous-time voltage controlled oscillator (VCO) quantizer, and a feedback loop coupled between the input and the output. The second continuous-time sigma-delta modulator is cascaded with the first continuous-time sigma-delta modulator. The summation element has inputs coupled to outputs of the first and second continuous-time sigma-delta modulators.

Methods/systems employ randomly jittered under-sampling to reduce a sampling rate required to estimate the amplitude of high-frequency signals in circuit breakers, power meters, and other digital signal processing applications. The methods/systems can greatly reduce the nominal sampling rate for applications where RMS, peak and mean estimates of the signal are desired for both the entire band-limited signal and separate estimates for each frequency component. This can in turn result in large cost savings, as less complex and thus less expensive controllers and related components may be used to perform the sampling. As well, the methods/systems herein can provide reasonably accurate waveform estimates that allow additional cost savings in bill of materials (BOM) and printed circuit board assembly (PCBA) footprint and real-estate by eliminating the need for certain analog components, such as signal conditioning components.

Various embodiments disclosed herein relate to adaptive clock signal management, and more specifically, to transitioning between clock frequencies to convert analog signals to digital signals at dynamic sampling rates. In an example embodiment, a device including an analog-to-digital converter (ADC) and a control circuit coupled to the ADC is provided. The ADC is configured to receive a first analog signal, receive a first clock signal, and generate a first set of digital values corresponding to the first analog signal based on the first clock signal. The control circuit is configured to determine that a change in the first set of digital values satisfies a first threshold value and increase the first clock signal from a first frequency to a second frequency in response to determining that the change in the first set of digital values satisfies the first threshold value.

This disclosure describes apparatuses, methods, and techniques that enable a computing device to support a dynamic range of audio quality, varying bandwidths, varying sampling rates, numerous effective number of bits (ENOBs) resolutions, conserve power during an overall usage of the computing device, and enhance a user experience. To do so, the computing device utilizes a reconfigurable analog-to-digital converter (ADC). The reconfigurable ADC includes a successive-approximation-register (SAR) ADC, a noise-canceling circuit, and a noise-shaping circuit. The reconfigurable ADC can selectively operate in different modes of operation, in part, by enabling or disabling the noise-canceling circuit and the noise-shaping circuit.