An apparatus for canceling a self-interference signal and a transceiver including the same are disclosed. The transceiver may include an antenna; a circulator transmitting a portion of a transmit signal to the antenna and transmitting a receive signal received through the antenna to a receiver; and a self-interference signal canceling unit receiving a first signal, which is a portion of the transmit signal, and physically copying a self-interference signal generated by the antenna and the circulator to generate an estimation signal of the self-interference signal.

Radio frequency switch circuitry is disclosed having first and second port terminals, a switch branch having first and second branch terminals, and a branch control terminal, wherein the switch branch is configured to pass an RF signal between the first and second branch terminals in an on-state and block the RF signal from passing between the first and second branch terminals in an off-state in response to a control signal that is coupled with the RF signal and received at the first port terminal. Control signal decoupling circuitry has a control signal input terminal coupled to the first port terminal to receive the control signal coupled to the RF signal and a control signal output terminal coupled to the branch control terminal, wherein the control signal decoupling circuitry is configured to decouple the control signal from the RF signal and provide the control signal to the branch control terminal.

The present disclosure provides an electronic module including a circuit including a transmitting part and a receiving part physically separated from the transmitting part. The electronic module also includes an element isolated from the circuit and configured to block electrical interference between the transmitting part and the receiving part.

A high-frequency switch module (10) includes a switch element (20) and an inductor (30). The switch element (20) includes a Hi band common terminal (P10), a Low band common terminal (P20), a plurality of selection target terminals (P11 to P14) that are selectively connected to the common terminal (P10), and a plurality of selection target terminals (P21 to P24) that are selectively connected to the common terminal (P20). The inductor (30) is connected between a first selection target terminal (P14) of the selection target terminals (P11 to P14) and a selection target terminal (P21) of the selection target terminals (P21 to P24). The selection target terminal (P14) and the selection target terminal (P21) are simultaneously used terminals that are used for electric paths through which transmission or reception using a plurality of communication bands is performed at the same time.

An apparatus includes one or more field effect transistors configured as a switch. Each of the one or more field effect transistors comprises one or more source diffusions, one or more drain diffusions, and one or more gate fingers. Each of the one or more gate fingers is disposed between a source diffusion and a drain diffusion. A first electrical connection to the one or more source diffusions is made using one or more source electrodes that extend from a first end for a first length along a long axis of the source diffusions. A second electrical connection to the one or more drain diffusions is made using one or more drain electrodes that extend from a second end for a second length along a long axis of the drain diffusions. The first length of the one or more source electrodes and the second length of the one or more drain electrodes are generally selected to avoid juxtaposition of the one or more source electrodes and the one or more drain electrodes.

A wireless transceiver includes: a switching amplifier having first, second and power ports; and a current provider. The current provider provides a current to the power port, and further provides an impedance to the power port such that an impedance of the switching amplifier at the second port matches an impedance of an antenna coupled to the second port. The switching amplifier simultaneously amplifies a transmit signal input received at the first port to generate an output signal at the second port for receipt by the antenna, and mixes a receive signal received at the second port from the antenna with the transmit signal input to generate, at the power port, another output signal having a frequency lower than that of the receive signal.

A high throw-count multiple-pole FET-based RF switch architecture that provides good RF performance in terms of insertion loss, return loss, isolation, linearity, and power handling. A common port RFC is coupled along a common path to multiple ports RFn. Embodiments introduce additional common RF path branch isolation switches which are controlled by state dependent logic. The branch isolation switches help to isolate the unused branch ports RFn and the unused portion of the common path from the active portion of the common path, and thereby reduce the reactive load attributable to such branches that degrades RF performance of the ports RFn closer to the common port RFC. The branch isolation switches can also be used to reconfigure the switch architecture for a multiplex function as well as separate switch path banks for re-configurability of purpose, tuning, or varying switch throw counts and packaging options.

An operation method of an in-band full duplex (IFD) transceiving apparatus including a receiving end, a transmitting end, a digital self-interference cancellation (DSIC) processing unit, and a digital SI cancellation unit may comprise generating, by the DSIC processing unit, signal shaping coefficients for wave shaping of a signal of the transmitting end; generating, by the DSIC processing unit, channel estimation coefficients for cancellation of a self-interference signal in a reception signal of the receiving end; forming, by the DSIC processing unit, a transmission signal based on the signal shaping coefficients; and generating, by the DSIC processing unit, a control signal for cancellation of the self-interference signal in the reception signal based on the channel estimation coefficients.

A linearization circuit reduces intermodulation distortion in an amplifier that includes a first stage and a second stage. The linearization circuit receives a first signal that includes a first frequency and a second frequency and generates a difference signal having a frequency approximately equal to the difference of the first frequency and the second frequency, generates an envelope signal based at least in part on a power level of the first signal, and adjusts a magnitude of the difference signal based on the envelope signal. When the amplifier receives the first signal at an input terminal, the first stage receives the adjusted signal, and the second stage does not receive the adjusted signal, intermodulation between the adjusted signal and the first signal cancels at least a portion of the intermodulation between the first frequency and the second frequency from the output of the amplifier.

A linearization circuit that reduces intermodulation distortion in an amplifier output receives a first signal that includes a first frequency and a second frequency and generates a difference signal having a frequency approximately equal to the difference of the first frequency and the second frequency. The linearization circuit generates an envelope signal based at least in part on a power level of the first signal and adjusts a magnitude of the difference signal based on the envelope signal. When the amplifier receives the first signal at an input terminal and the adjusted signal at a second terminal, intermodulation between the adjusted signal and the first signal cancels at least a portion of the intermodulation products that result from the intermodulation of the first frequency and the second frequency.