Patent classifications
H04J3/0641
Multi-clock synchronization in power grids
Disclosed are methods and systems to improve the time synchronization of power distribution systems and/or other distributed device networks. The disclosure relates to nesting selection algorithms to elect a grand master clock from among groups of devices in a network.
METHOD FOR CLOCK SYNCHRONIZATION OF AN INDUSTRIAL INTERNET FIELD BROADBAND BUS
Disclosed is a method for clock synchronization of an industrial internet field broadband bus, wherein the method is applicable to an industrial internet field broadband bus architecture system including a bus controller and at least one bus terminal, the bus controller is connected with the bus terminal over a two-wire data transfer network, and the method includes steps of: electing one of the bus controller and the bus terminal as a best master clock; determining whether an IP address of the device of the best master clock is the same as an IP address of the bus controller; if so, then determining the bus controller as a master device of clock synchronization, and transmitting by the bus controller a synchronization message to the bus terminal for clock synchronization; and otherwise, returning to the step of electing one of the bus controller and the bus terminal as the best master clock.
Communication apparatus, communication system, communication method, and computer readable medium
A communication system (500) includes a plurality of communication apparatuses (100) and selects from the plurality of communication apparatuses (100), a grandmaster that is to be a standard of time. A difference calculation unit (110), when receiving a synchronization message that includes time of the grandmaster from the grandmaster, calculates a time difference between the time of the grandmaster and time of the communication apparatus (100). A correction unit (120) changes count speed of a time counter that counts the time of the communication apparatus (100) in a way that the time of the communication apparatus (100) synchronizes with the time of the grandmaster at a time when a time correction period that is specified beforehand elapses, based on the time difference.
METHOD FOR SYNCHRONIZING TIME IN MULTIPLE TIME DOMAINS, AND APPARATUS IMPLEMENTING THE SAME METHOD
A method of synchronizing time across a plurality of time domains between a master node and a slave node is provided. The method comprises transmitting, by the master node, a reference time indicated by a hardware clock of the master node to the slave node, synchronizing, by the slave node, a hardware clock of the slave node to the reference time indicated by the hardware clock of the master node, transmitting, by an offset clock layer of the master node, an offset of a first time domain among the plurality of time domains to an offset clock layer of the slave node, and obtaining, by the PTP layer of the slave node, a time in the first time domain by applying the offset of the first time domain to a reference time indicated by the hardware clock of the slave node.
METHOD TO ELIMINATE CLOCK SYNCHRONIZATION FROM UNDESIRED CLOCK SOURCES
In one embodiment, methods for monitoring devices within a network by a controller are described. The method may include receiving a first request from a first device to authenticate a role of the first device as a grandmaster in a precision time protocol (PTP). Additionally, the method may include granting the first request designating the role of the first device as the grandmaster. The method may further include receiving a second request from a second device to authenticate that a clock announce message is from an authorized grandmaster. Additionally, the method may include determining whether the first device is authorized to send the clock announce message to the second device and, based on the determining, sending a message granting or denying permission for the first device to sync with the second device.
Wireless audio synchronization
An audio distribution system includes an audio source; and a plurality of audio playback devices in communication with each other and with the audio source. A group of the audio playback devices are arranged to render audio content provided by the audio source in synchrony. One of the audio playback devices within the group is configured as an audio master which distributes audio content from the audio source to the other audio playback devices within the group, and one of the plurality of audio playback devices, other than the audio master, is configured as a clock master, which distributes clock information that the group of audio playback devices synchronizes to.
METHOD AND TIME SYNCHRONIZATION (TS) NODE FOR ENABLING EXTENDED HOLDOVER TIME
The present disclosure provides a method and time synchronization node for enabling extended holdover time. The method comprises: detecting whether the TS node loses time synchronization with its master TS node or not; and transmitting a first announce message comprising a first indicator to one or more slave TS nodes in response to detecting that the TS node loses the time synchronization with its master TS node, wherein the first indicator indicates a holdover time budget for enabling extended holdover time at the one or more slave TS nodes.
APPARATUS AND MECHANISM TO SUPPORT MULTIPLE TIME DOMAINS IN A SINGLE SOC FOR TIME SENSITIVE NETWORK
A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.
NETWORK SWITCH AND CIRCUIT BOARD WHERE PRECISION TIME PROTOCOL MODULE IS USED
A network switch can include a precision time protocol (PTP) module and a circuit board. The PTP module can provide a first clock signal and include a predetermined interface. The circuit board can include a socket, an oscillator and a selection unit. The socket can be inserted by the predetermined interface to receive the first clock signal. The oscillator can provide a second clock signal. The selection unit can include a first terminal, a second terminal, an output terminal and a selection terminal. The first terminal can receive the first clock signal when the predetermined interface is inserted into the socket. The second terminal can receive the second clock signal. The output terminal can output one of the first clock signal and the second clock signal. The selection terminal can receive a selection signal to control the output terminal to output the first clock signal or the second clock signal.
SYSTEMS AND METHODS FOR SYNCHRONIZING DEVICE CLOCKS
A media system, method, and a computer program product for synchronizing device clocks including a plurality of devices having device clocks, where each device is capable of independently selecting a primary clock device from the plurality of devices to coordinate clock synchronization of the remaining devices, e.g., secondary devices. Each device can utilize the same criteria or set of rules to select the primary clock device from among the plurality of devices after an initial exchange of data during a discovery phase. The selection of the primary clock device can be based on random or arbitrary selection, or based on at least one devices characteristic exchanged within the data obtained during the discovery phase. Once selected, the primary clock device coordinates a clock synchronization sequence with each secondary device until each secondary device clock is synchronized to within a predetermined threshold with the primary clock of the primary clock device.