Calibration of devices communicating on a shared data bus may improve data integrity on the shared data bus by reducing duty cycle distortion. Duty cycle distortion may be reduced by adjusting timing of a transceiver in a device for communicating on the shared data bus using calibration codes. The calibration codes may be loaded into memory and used to reconfigure the transceiver timing on the shared data bus with reconfiguration occurring within one or more unit-intervals of time. The calibration code may be used, for example, to adjust a PMOS or NMOS trim circuit at the transceiver.

The present disclosure relates to flexible-Ethernet data processing methods and devices. One example method includes acquiring a to-be-switched first client service flow, where the first client service flow is a service flow suitable for transmission on a flexible Ethernet, performing first rate adaptation from a source clock domain to a target clock domain on the first client service flow to obtain a second client service flow that matches the target clock domain, and performing serial-to-parallel conversion on the second client service flow in the target clock domain to obtain a parallel client slot flow.

A system (100) comprising: a first unit (104) and one or more second units (104). The first unit (102) comprises: a timing reference (114) configured to provide a master-timing-reference-signal; a master time block configured to provide a master-time-signal (117) for the first unit (102) based on the master-timing-reference-signal; and a first interface (122) configured to: receive timestamped-processed-second-RF-signals from the one or more second units (104); and provide a first-unit-timing-signal (262) to the one or more second units (104) based on the master-time-signal. The one or more second units (104) each comprise: a slave time block (141) configured to: determine a slave-time-signal (142) for the second unit (104) based on the master-timing-reference-signal; determine one or more second-timing-values based on the slave-time-signal; determine an adjustment-time based on the first-unit-timing-signal received from the first unit (102) and the second-timing-values; and adjust the slave-time-signal based on the adjustment-time.

An automotive communication system includes multiple communication devices and a processor. The communication devices are configured to be installed in a vehicle and to communicate with one another over point-to-point Ethernet links. In each Ethernet link, a first communication device serves as a link master that is configured to set a clock signal for the link, and a second communication device serves as a slave that is configured to synchronize to the clock signal set by the first communication device. The communication devices are configured to receive data from sensors and to transmit the data over the Ethernet links. The processor is configured to receive the data from the communication devices over the Ethernet links, to synchronize the data originating from the multiple sensors to a common time-base based on link-specific clock-signal synchronization achieved on each of the links by each link master, and to process the synchronized data.

Techniques that provide link establishment between a radio equipment controller (REC) and a radio equipment (RE) in a fronthaul network are described herein. In one embodiment, a method includes performing, Common Public Radio Interface (CPRI) Layer 1 (L1) link auto-negotiation operations to establish a CPRI link between the REC and RE. A proxy slave may achieve a hyper frame number (HFN) synchronization with the REC at a link bit rate for a first CPRI bit stream and communicate the first CPRI bit stream and the link bit rate to a proxy master. The proxy master may communicate a second CPRI bit stream to the proxy slave to transmit to the REC. The L1 link auto-negotiation operations are completed and CPRI link is established between the REC and the RE when the REC achieves a HFN synchronization for the second CPRI bit stream.

The present disclosure provides techniques for measuring and compensating for clock drift errors in time-aware networks and time-sensitive applications, where a time-aware system (TAS) measures clock drift, and compensates for the measured clock drift, and makes predictions of future clock drift values based on history and other physical measurements. Existing messages used for measuring link delay and/or used for time synchronization can be used for frequency measurement (and thus clock drift measurement), and this measured drift can be applied as a correction factor whenever synchronization is determined and/or used. The predicted clock drift rate can be based on various probability distributions including linear, Kalman filters, and/or others. Other embodiments may be described and/or claimed.

A controller includes circuitry configured to: synchronize a master clock with an external global clock and set a master time based on the master clock; synchronize a controller clock with the master clock and perform time synchronization to synchronize a controller time based on the controller clock with the master time; transmit controller time data indicating the synchronized controller time to at least one local device; set a plurality of time windows corresponding to a plurality of clock cycles of a clock signal for the time synchronization; determine whether one clock cycle of the plurality of clock cycles has started within one time window of the plurality of time windows, the one time window corresponding to the one clock cycle; and suspend the time synchronization corresponding to the one clock cycle, in response to determining that the one clock cycle has not started within the one time window.

A first network device may receive, from a second network device, a clock quality indication that is associated with a clock of the second network device, wherein the clock of the second network device is a reference clock for a network that includes the first network device and the second network device. The first network device may determine, based on a clock signal of the second network device, that a quality metric of the clock does not satisfy a threshold. The first network device may provide, to the second network device, a clock fault notification to cause the second network device to downgrade the clock quality indication transmitted by the second network device. The first network device may select a new reference clock for the first network device based on receiving the downgraded clock quality indication from the second network device.

Techniques that provide link auto-negotiation between a radio equipment controller (REC) and a radio equipment (RE) are described herein. In one embodiment, a method includes performing, by a proxy master, a Common Public Radio Interface (CPRI) Layer 1 (L1) link auto-negotiation with a RE to achieve a L1 synchronization between the proxy master and the RE at a link bit rate; communicating the link bit rate from the proxy master to a proxy slave; performing, by the proxy slave, a CPRI L1 link auto-negotiation with a REC to determine whether a L1 synchronization between the proxy slave and the REC is achieved, wherein if the L1 synchronization is achieved, the link bit rate is a common matching link bit rate achieved; and upon the common matching link bit rate being achieved, establishing a CPRI link between the REC and the RE using the common matching link bit rate.

Techniques that provide link auto-negotiation between a radio equipment controller (REC) and a radio equipment (RE) are described herein. In one embodiment, a method includes performing, by a proxy master, a Common Public Radio Interface (CPRI) Layer 1 (L1) link auto-negotiation with a RE to achieve a L1 synchronization between the proxy master and the RE at a link bit rate; communicating the link bit rate from the proxy master to a proxy slave; performing, by the proxy slave, a CPRI L1 link auto-negotiation with a REC to determine whether a L1 synchronization between the proxy slave and the REC is achieved, wherein if the L1 synchronization is achieved, the link bit rate is a common matching link bit rate achieved; and upon the common matching link bit rate being achieved, establishing a CPRI link between the REC and the RE using the common matching link bit rate.