Embodiments of a method and a device are disclosed. In an embodiment, a method for operating a wired communications device involves including a frame boundary bit sequence and a random data sequence as a preamble of a bit stream, encoding the bit stream into an encoded bit stream, and transmitting the encoded bit stream using the wired communications device.

Embodiments relate to optical transport technologies, and more specifically, to a clock transmission method. Under this method, a first optical data unit (ODU) container can be obtained. Phase discrimination can be performed on an obtained first clock and a first ODU clock of a transmit end, to generate a first PD value. The first

PD value can then be inserted into an overhead of the first ODU container. The first ODU container can be encapsulated into a second ODU container, and the second ODU container can be sent. A rate of the second ODU container is higher than a rate of the first ODU container. The first PD value is transmitted in the first ODU container which is not decapsulated in a subsequent transmission process. Therefore, final recovery of the first clock is not affected, so that a deviation between a finally recovered clock and the first clock is greatly reduced.

Techniques are disclosed for determining propagation delay of a first path and or of a second path which connect a first transceiver unit associated with a first clock to a second transceiver unit associated with a second clock in a communications network, based on a first time reference representing a time of transmission of a first signal from the first transceiver unit, a second time reference representing the time of receipt of the first signal at the second transceiver unit, a third time reference representing a time of transmission of a reply to the second signal from the second transceiver unit, and a fourth time reference representing the time of receipt of the reply to the second signal at the first transceiver unit.

A communications network delay variation smoothing method, an apparatus, and a system are disclosed. The method includes: clearing, by a local device, a forward delay threshold and a reverse delay threshold when an initialization time starts; and when determining that a maximum value between a real-time forward delay value corresponding to a current service flow fragment and a reverse delay threshold corresponding to the current service flow fragment is greater than a current value of the forward delay threshold, replacing the current value of the forward delay threshold with the maximum value. In this way, after the initialization ends, a delay threshold after the initialization ends is determined and is applied to delay compensation, thereby significantly reducing a bi-directional asymmetric delay variation, and avoiding a problem of abnormal user communication that is caused when the variation exceeds a limit.

A method is described and in one embodiment includes detecting a transition of a data signal comprising a data packet received at a circuit while the circuit is in a first hysteresis mode; placing the circuit in a second hysteresis mode subsequent to the detecting; and returning the receiver to the first hysteresis mode subsequent to completion of receipt of the data packet to await receipt of a next data packet. In certain embodiments, the first hysteresis mode is a high hysteresis mode and the second hysteresis mode is a standard hysteresis mode. In some embodiments, a level of each of the first and second hysteresis modes is dynamically tunable.

The present disclosure relates to a method and an apparatus for TDMA slot synchronization and calibration of a master and a slave. The method includes: receiving a synchronizing frame from a master by at least one slave, in which the synchronizing frame includes a first count value of a timing counter of the master; analysing the synchronizing frame by the at least one slave to acquire the first count value; adjusting a TDMA slot of each slave according to the first count value and a second count value of a timing counter of the slave to synchronize the TDMA slot of the slave with a TDMA slot of the master. It can be seen that the synchronization is realized by directly using the respective clock sources of the master and the slave, without addition of the clock source of the RTC or the GPS module, thus reducing the cost and improving the accuracy.

Solution for reducing timing uncertainty is provided. The solution means for receiving data in a first clock domain; means for selecting in the first clock domain a data unit to be a frame starting point and transmitting the information on the selection to a frame counter in a second clock domain; means for performing to the data in a coding/decoding unit coding or decoding, the coding/decoding unit several clock domains; means for obtaining at the output of the coding/decoding unit the position of the selected frame starting point; and means for determining timing of the correct frame starting point of the coded/decoded data utilizing the obtained position of the selected frame starting point and the information in the frame counter.

Disclosed herein are systems and methods for clock sustain in a two-wire communication systems and applications thereof. In some embodiments, in a clock sustain state, slave nodes with processors and digital to analog converters (DACs) may be powered down efficiently in the event of lost bus communication. For example, when the bus loses communication and a reliable clock cannot be recovered by the slave node, the slave node may enter the sustain state and, if enabled, signals this event to a general purpose input/output (GPIO) pin. In the clock sustain state, the slave node phase lock loop (PLL) may continue to run for a predetermined number of SYNC periods, while attenuating the inter-integrated circuit transmit (I2S DTXn) data from its current value to 0. After the predetermined number of SYNC periods, the slave node may reset and reenter a power-up state.

Systems and methods presented herein enhance WiFi communications in a RF band where conflicting LTE signaling exists. In one embodiment, a system includes a processor operable to detect the WiFi communications between a UE and a wireless access point of a WiFi network, to identify errors in the WiFi communications, and to determine a periodicity of the errors based on the LTE signaling structure. The system also includes an encoder communicatively coupled to the processor and operable to encode the WiFi communications with error correction, and to change the error correction based on the periodicity of the errors in the WiFi communications.

Systems and methods presented herein provide for an LTE wireless communication system operating in a Radio Frequency (RF) band with a conflicting wireless system. The LTE system includes an eNodeB operable to detect a plurality of UEs in the RF band, to generate LTE frames for downlink communications to the UEs, and to time-divide each LTE frame into a plurality of subframes. The eNodeB is also operable to condense the downlink communications into a first number of the subframes that frees data from a remaining number of the subframes in each LTE frame, and to burst-transmit the first number of the subframes of each LTE frame in the RF band.