This application discloses a clock synchronization mode indication method and a communication apparatus, and relates to the communications field, so that a communication device in a 5G communication system obtains a clock synchronization mode. The clock synchronization mode indication method includes: A session management function network element obtains first indication information, where the first indication information indicates a clock synchronization mode used in a communication system in which a terminal device and a user plane function network element are located. The session management function network element sends the first indication information to the terminal device.

Provided is a transmission circuit with which it is possible to facilitate error correction of burst errors without increasing the processing load in multiframes configured from a plurality of OTN frame signals. This transmission circuit is provided with: a transmission-side signal recognition unit for detecting MFAS and recognizing the order of N number of OTN frame signals; an intra-multiframe sequence conversion unit for converting the sequence of data signals inside the multiframe in response to the recognized order; a transmission-side rearranging unit for consolidating the sequentially converted data signals into lengths equal to those of the OTN frame signals and creating N number of quasi-OTN frame signals; and a transmission unit for transmitting the multiframes configured from the N number of quasi-OTN frame signals.

A synchronization apparatus capable of reducing the effect of the fluctuations in synchronization signals that are caused when the synchronization signals are received through a network are provided. A synchronization apparatus (20) according to the present invention receives a synchronization signal transmitted from a synchronization signal source (10) through a network. The synchronization apparatus (20) includes a frequency synchronization unit (21) that performs frequency synchronization based on a received synchronization signal, and outputs a frequency synchronization signal, a phase synchronization unit (23) that performs phase synchronization based on a synchronization signal transmitted from the synchronization signal source (10) through a network, and outputs a phase synchronization signal, and a phase synchronization control unit (22) that generates an offset value by using a phase difference between the frequency synchronization signal and the phase synchronization signal, and corrects a phase of the frequency synchronization signal by using the offset value.

Techniques that provide link establishment between a radio equipment controller (REC) and a radio equipment (RE) in a fronthaul network are described herein. In one embodiment, a method includes performing, Common Public Radio Interface (CPRI) Layer 1 (L1) link auto-negotiation operations to establish a CPRI link between the REC and RE. A proxy slave may achieve a hyper frame number (HFN) synchronization with the REC at a link bit rate for a first CPRI bit stream and communicate the first CPRI bit stream and the link bit rate to a proxy master. The proxy master may communicate a second CPRI bit stream to the proxy slave to transmit to the REC. The L1 link auto-negotiation operations are completed and CPRI link is established between the REC and the RE when the REC achieves a HFN synchronization for the second CPRI bit stream.

A method includes computing electrical phase of electrical metering devices including obtaining data indicating zero-crossing times at first and second metering devices. A time difference between the zero-crossing times may be determined. In a first example, the time difference may be based at least in part on calculations involving a first value of a first free-run timer on a first metering device, a second value of a second free-run timer on a second metering device, the time of reception of a packet, and a latency defined by a time taken for the packet to propagate through at least one layer of at least one of the first metering device and the second metering device. A phase difference between the first zero-crossing and the second zero-crossing may be determined, based at least in part on the determined time difference.

An optical transmission device includes: a receiver configured to receive a signal including data; a generator configured to generate an output clock to output the data based on a signal clock synchronized with the signal; and a controller configured to control a frequency of the output clock based on a first amount of the data so that the output clock follows a clock of a transmission source of the data.

A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

An audio system, method, and computer program product for synchronizing device clocks. The systems, methods and computer program product can establish a first isochronous data stream between a peripheral device and a first device and establish a second isochronous data stream between the first device and a second device to send data between the first and second device. As the two data streams may rely on two different device clocks, e.g., one clock which defines the timing for the first isochronous data stream and a second clock which defines the timing for the second isochronous data stream, the systems, methods, and computer program disclosed herein are configured to maintain synchronization and/or synchronize the first clock with the second clock to prevent data loss due to clock drift.

According to some embodiments, a master device sends synchronization packets to one or more slave devices, and does so periodically based on a master clock signal having a master clock frequency. At each of the slave devices, an algorithm estimates the master clock frequency based on the timing of synchronization packet arrivals the slave device. The algorithm may estimate the master clock frequency using both the currently-observed timing of synchronization packet arrivals and the history of previous synchronization packet arrivals (e.g., previously-observed timing of synchronization packet arrivals). Based on the estimated master clock frequency, each of the one or more slave devices can update the frequency of their respective slave clock signal (e.g., using a frequency offset) to match that of the estimated master clock frequency.

A cross-domain clock synchronization method, device and system and a computer storage medium, which are applied to a cross-domain synchronization network. A Path Calculate Element (PCE) exchanges a clock synchronization type with a controller participating in clock synchronization path calculation to match the clock synchronization type supported by the PCE and the controller; the PCE acquires physical topological information of the cross-domain synchronization network; the PCE acquires synchronization information of synchronization nodes of the cross-domain synchronization network and/or hop number information between the synchronization nodes; the PCE calculates a clock synchronization path of the cross-domain synchronization network according to the physical topological information as well as the synchronization information and/or the hop number information; and the PCE sends the clock synchronization path to the controller according to the physical topological information to enable the controller to send a clock synchronization instruction to synchronization nodes on the clock synchronization path.