Embodiments for providing reference signal generation redundancy in wireless communications systems are disclosed. To avoid a single point of failure in reference signal generation that could cause components relying on the reference signal to not operate properly, the reference signal generation circuits disclosed herein include a plurality of reference signal generation modules. One reference signal generation module is configured as the master reference signal generation module to generate a master reference signal distributed in the wireless communication system. The other reference signal generation modules are configured as slave reference signal generation modules. If a failure is detected in the generation of the master reference signal in the master reference signal generation module, another slave reference signal generation module is reconfigured to be the new master reference signal generation module to generate the master reference signal. In this manner, the reference signal generation circuit does not have a single point of failure.

A system includes a first node that generates a first clock signal having a frequency, generates a plurality of data packets, modifies the data packets to include data indicative of time and phase information associated with the first node, and transmits the data packets. A second node receives the plurality of data packets and the first clock signal, determines the time and phase information based on the plurality of data packets, determines the frequency based on the first clock signal, and generates at least one of a second clock signal and a local time based on the time and phase information and the frequency of the first clock signal.

A sensor synchronization system for an autonomous vehicle is described. Upon initializing a master clock on a master processing node for a sensor apparatus of the autonomous vehicle, the system determines whether an external timing signal is available. If the signal is not available, the system sets the master clock using a local timing signal from a low-power clock on the autonomous vehicle. Based on a clock cycle of the master clock, the system propagates timestamp messages to the sensors of the sensor apparatus, receives sensor data, and formats the sensor data based on the timestamp messages.

Embodiments for providing reference signal generation redundancy in distributed antenna systems (DASs) are disclosed. To avoid a single point of failure in reference signal generation that could cause components relying on the reference signal to not operate properly, the reference signal generation circuits disclosed herein include a plurality of reference signal generation modules. One reference signal generation module is configured as the master reference signal generation module to generate a master reference signal distributed in the DAS. The other reference signal generation modules are configured as slave reference signal generation modules. If a failure is detected in the generation of the master reference signal in the master reference signal generation module, another slave reference signal generation module is reconfigured to be the new master reference signal generation module to generate the master reference signal. In this manner, the reference signal generation circuit does not have a single point of failure.

A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect OSI model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

Various embodiments relate to a network node and method thereof including a high stability oscillator and a holdover phase-locked loop (PLL) wherein the holdover PLL is configured to perform a holdover function by receiving a system clock signal, disciplining the high stability oscillator using the system clock signal to generate a local reference signal, and providing the local reference signal as the system clock signal when the system clock signal becomes unavailable.

A system and method for clock phase alignment at a plurality of line cards over a backplane of a communication system. Phase adjustments are continually made for the clock signals at the line cards by dynamically measuring the propagation delay between the timing device and each of the plurality of line cards and continuously communicating the appropriate phase adjustment to each of the plurality of line cards.

A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect OSI model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

A network element for distributing timing information includes a signal interface for receiving satellite signals transmitted by a satellite system and a processing system for producing the timing information based on the satellite signals and on assistance information received from a data transfer network. The network element transmits the timing information to the data transfer network in accordance with a timing transfer protocol. At a start-up, the network element requests a dynamic host configuration protocol server to send host configuration data containing a protocol address to be associated with the network element. The network element reads, from the host configuration data, information enabling the network element to get aware of the assistance information and obtains the assistance information in accordance with the read information. Thus, the dynamic host configuration protocol server enables the network element to operate as a network-assisted source of satellite-based timing.

A 100BASE-TX transceiver includes a receive (RX) circuit, a transmit (TX) circuit, a clock generator circuit, a clock and data recovery (CDR) circuit, and a clock multiplexer circuit. The RX circuit receives an input data to generate an RX data. The TX circuit transmits a TX data according to a TX clock, to generate an output data. The clock generator circuit generates an output clock. The CDR circuit generates an RX recovered clock according to the RX data. The clock multiplexer circuit receives the output clock and the RX recovered clock, and outputs the TX clock that is selected from the output clock and the RX recovered clock.