A system that switches between a clock signal from a first line card and a clock signal from a second line card based on information transmitted from the first line card and the second line card on timing signals is presented. Some methods include receiving a first pulse-width modulated clock signal from a first line card, the first pulse-width modulated clock signal including information regarding the status of the first line card; receiving a second pulse-width modulated clock signal from a second line card, the second pulse-width modulated clock signal including information regarding the status of the second line card; producing a clock signal from the first pulse-width modulated clock signal; and switching to producing the clock signal from the second pulse-width modulated clock signal based on the information in the first pulse-width modulated clock signal.

A microcontroller includes a packet matching circuit, a hardware timer circuit, and a processor. The packet matching circuit is configured to match contents of received packets to the microcontroller and identify whether a packet has been received. The hardware timer circuit is configured to provide a synchronization timestamp based on a signal from the packet matching circuit that a synchronization packet has been matched, and provide a follow-up timestamp based on a signal from the packet matching circuit that a follow-up packet has been matched after reception of the synchronization packet. The processor is configured to adjust a clock base to determine a synchronized clock base based upon the synchronization timestamp and upon the follow-up timestamp.

In general, various aspects of the techniques described in this disclosure provide time synchronization for encrypted traffic in a computer network. In one example, the disclosure describes an apparatus, such as a network device, having a control unit for a network device in a computerized network having a topology of network devices; and a forwarding unit operative to determine a release time for sending a synchronization packet in accordance with a time synchronization protocol; modify the synchronization packet to include a release timestamp specifying the release time; sending a time value via sideband data associated with the synchronization packet, wherein the time value is based on the release time specified by the release timestamp; and schedule transmission of the synchronization packet for a time corresponding to the time value in the sideband data, the synchronization packet to be transmitted to a destination network device.

A system for a network of one or more off-board subsystems is provided for controlling automobile subsystems such as vehicle lighting. Such a system may be compatible with a universal asynchronous receiver transmitter (UART) interface and it may address timing issues by using a protocol having a synchronization frame (sync frame) such that a clock signal may be recovered from the sync frame sent by an off-board master device 202, such as a microcontroller unit 208, to a satellite/slave 211 device. Such a protocol permits elimination of a crystal clock oscillator and phase-locked loop located at satellite, thereby dispensing with an otherwise significant cost.

In one embodiment, a system receives a number of times from a number of time sources including sensors and real-time clocks (RTCs), wherein the sensors are in communication with an autonomous driving vehicle (ADV) and the sensors include at least a GPS sensor. The system generates a difference histogram based on a time for each of the time sources for a difference between a time of the GPS sensor and a time for each of the other sensors and RTCs. The system ranks the sensors and RTCs based on the difference histogram. The system selects a time source from one of the sensors or RTCs with a least difference in time with respect to the GPS sensor. The system generates a timestamp based on the selected time source to timestamp sensor data for a sensor unit of the ADV.

In one embodiment, a network interface card device includes communication interfaces to provide data connection with respective local devices configured to run respective clock synchronization clients, at least one network interface to provide data connection between a packet data network and ones of the local devices, and a hardware clock to maintain a time value, and serve the clock synchronization clients.

A media system, method, and a computer program product for synchronizing device clocks including a plurality of devices having device clocks, where each device is capable of independently selecting a primary clock device from the plurality of devices to coordinate clock synchronization of the remaining devices, e.g., secondary devices. Each device can utilize the same criteria or set of rules to select the primary clock device from among the plurality of devices after an initial exchange of data during a discovery phase. The selection of the primary clock device can be based on random or arbitrary selection, or based on at least one devices characteristic exchanged within the data obtained during the discovery phase. Once selected, the primary clock device coordinates a clock synchronization sequence with each secondary device until each secondary device clock is synchronized to within a predetermined threshold with the primary clock of the primary clock device.

A PHY chip for a synchronous Ethernet system includes N network input/output (I/O) ports, a first external recovered clock input, a first recovered clock output, and a first clock multiplexer having a plurality of data inputs, a select input, and an output coupled to the first recovered clock output, at least one of the data inputs coupled to a first recovered clock from a respective one of the N network I/O ports, a first additional data input coupled to the first external recovered clock input.

Embodiments describe monitoring network activity and behavior of authorized clocks to identify suspicious activity, and in response, removing a clock for an authorized clock list. In one embodiment, a network monitor detects changes in profiles corresponding to the authorized clocks such as a disconnecting from a port, changing a network location, unexpected changes in the clock signal, changes to the clock ID or MAC address, and the like. If the network monitor deems these changes suspicious, it removes the clock from the authorized clock list. When the current master clock fails, the PTP endpoints select a new master clock only if that clock is included in the authorized clock list. In this manner, the network monitor can constantly update the authorized clock list to ensure it contains only clocks that have not been tampered with or replaced with rogue clocks.

A shared bus time interleaves 1 PPS signal and control and coordination information between a primary timing source and line cards that need to be synchronized using the 1 PPS signals. The shared bus utilizes 1 second frames divided into time slots. The 1 PPS signals are interleaved at predetermined locations in the frame so the delays introduced by interleaving the 1 PPS data in time can be precisely removed. While the bus is not being used for 1 PPS signals, the bus is available to send control and coordination information between the line cards and the primary timing source, avoiding the use of another system and increasing utilization of an available communication path.