A system that switches between a clock signal from a first line card and a clock signal from a second line card based on information transmitted from the first line card and the second line card on timing signals is presented. Some methods include receiving a first pulse-width modulated clock signal from a first line card, the first pulse-width modulated clock signal including information regarding the status of the first line card; receiving a second pulse-width modulated clock signal from a second line card, the second pulse-width modulated clock signal including information regarding the status of the second line card; producing a clock signal from the first pulse-width modulated clock signal; and switching to producing the clock signal from the second pulse-width modulated clock signal based on the information in the first pulse-width modulated clock signal.

Embodiments for providing reference signal generation redundancy in wireless communications systems are disclosed. To avoid a single point of failure in reference signal generation that could cause components relying on the reference signal to not operate properly, the reference signal generation circuits disclosed herein include a plurality of reference signal generation modules. One reference signal generation module is configured as the master reference signal generation module to generate a master reference signal distributed in the wireless communication system. The other reference signal generation modules are configured as slave reference signal generation modules. If a failure is detected in the generation of the master reference signal in the master reference signal generation module, another slave reference signal generation module is reconfigured to be the new master reference signal generation module to generate the master reference signal. In this manner, the reference signal generation circuit does not have a single point of failure.

In one embodiment, a method receives a first time from a network device. The first time is derived from a first timing source in a first domain. The method receives a second time in a second domain from a second timing source. A difference time value is calculated between the first time and the second time. The method then sends the difference time value to the network device where the network device uses the difference time value to send a delay value to other computing devices to synchronize timing of the other computing devices in the second domain. The other computing devices are configured to synchronize the respective time using the delay value with mobile network devices to allow timing synchronization between the mobile network devices.

A data processing unit includes a processing circuit that is configured to process data based on a value of a first parameter, a first operator that is selectively set to one of a first state and a second state that are physically identified, a second operator that is set to a physical state indicating the value of the first parameter, and a processor that is configured to set the value of the first parameter indicated by the physical state of the second operator in the processing circuit in a case where the first operator is in the first state at a time of activating the data processing unit, and set a value of the first parameter supplied from the information processing device in the processing circuit in a case where the first operator is in the second state at the time of activating the data processing unit.

A microcontroller includes a packet matching circuit, a hardware timer circuit, and a processor. The packet matching circuit is configured to match contents of received packets to the microcontroller and identify whether a packet has been received. The hardware timer circuit is configured to provide a synchronization timestamp based on a signal from the packet matching circuit that a synchronization packet has been matched, and provide a follow-up timestamp based on a signal from the packet matching circuit that a follow-up packet has been matched after reception of the synchronization packet. The processor is configured to adjust a clock base to determine a synchronized clock base based upon the synchronization timestamp and upon the follow-up timestamp.

A method and an apparatus determines a network device receiving a first signal and at least one second signal, wherein the first signal carries data to be sent through a first flexible Ethernet interface. A first physical layer clock is determined based on the first signal. A second physical layer clock is determined based on the at least one second signal or the first physical layer clock and the at least one second signal. The first physical layer clock or the second physical layer clock is used as a sending clock of a non-flexible Ethernet interface. The network device includes the first flexible Ethernet interface and the non-flexible Ethernet interface.

A shared bus time interleaves 1 PPS signal and control and coordination information between a primary timing source and line cards that need to be synchronized using the 1 PPS signals. The shared bus utilizes 1 second frames divided into time slots. The 1 PPS signals are interleaved at predetermined locations in the frame so the delays introduced by interleaving the 1 PPS data in time can be precisely removed. While the bus is not being used for 1 PPS signals, the bus is available to send control and coordination information between the line cards and the primary timing source, avoiding the use of another system and increasing utilization of an available communication path.

A control plane, available to all of the line cards in a system, is used to exchange time stamps to align the Time of Day counters in the master line cards. The master line cards are locked to a system clock distributed over the backplane by a timing card. The timing card is locked to timing of a slave line card that is synchronized with the grand master. Each master line card synchronizes updating its Time of Day counter based on a time stamp exchange and a local clock locked to the system clock and without the use of a 1 pulse per second signal.

A network element is provided that includes a signal interface for receiving satellite signals transmitted by a satellite system and a processing system for producing the timing information based on the satellite signals and on assistance information received from a data transfer network. The network element transmits the timing information to the data transfer network in accordance with a timing transfer protocol. At a start-up, the network element requests a dynamic host configuration protocol server to send host configuration data containing a protocol address to be associated with the network element. The network element reads, from the host configuration data, information enabling the network element to get aware of the assistance information and obtains the assistance information in accordance with the read information. Thus, the dynamic host configuration protocol server enables the network element to operate as a network-assisted source of satellite-based timing.

A device and a method for supporting clock transfer of multiple clock domains, where the device includes N phase frequency detectors, N filters, N clock reconstructors, and N clock domain interfaces, where N is an integer greater than or equal to two, the N clock domain interfaces are in a one-to-one correspondence with the N phase frequency detectors, the N filters, and the N clock reconstructors, the N phase frequency detectors are respectively connected to N clock sources, and at least two clock sources of the N clock sources are different. The foregoing device flexibly adapt to multiple different clock domains, implement that a single device simultaneously supports clock transfer of multiple clock domains, and flexibly satisfy user demands without adding or replacing devices.