Patent classifications
H04J3/0691
APPARATUS AND MECHANISM TO SUPPORT MULTIPLE TIME DOMAINS IN A SINGLE SOC FOR TIME SENSITIVE NETWORK
A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect OSI model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.
Optical transmission apparatus and optical reception apparatus
An optical transmission apparatus that accommodates client signals in a line signal, includes: an OPUn mapper unit that receives and maps the client signals; and a mapping control unit that determines the number of pieces of client data to be mapped to a payload portion and determines the timing to insert client data and information on the number of pieces of client data into the payload portion to control mapping performed in the OPUn mapper unit.
Frequency offset detection method and apparatus
Embodiments of the present invention provide a frequency offset detection method and apparatus. The frequency offset detection method in the present invention includes: calibrating a frequency offset of a clock signal output by a local crystal oscillator of a network element device, and performing frequency offset detection on a tracked reference clock signal by using the calibrated clock signal output by the local crystal oscillator. The embodiments of the present invention solve a problem in the prior art that a detection result for a frequency offset of a reference clock signal is inaccurate because of an existence of a frequency offset of a local crystal oscillator and a parameter drift caused by aging, thereby improving detection precision without replacing hardware.
Transmission apparatus and plug-in unit
A transmission apparatus includes: a first plug-in unit including: a clock generator to generate a first clock, a first frame-pulse generator to generate a first frame-pulse-signal based on the first clock; a detector to detect a phase-difference between a first phase of the first frame-pulse-signal and a second phase of a second frame-pulse-signal transmitted from other plug-in unit, and generate phase-difference information based on the phase-difference, and a first transmitter to transmit a control-signal including the phase-difference information to the other plug-in unit; and a second plug-in unit being the other plug-in unit, including: a receiver to receive the control-signal, a controller to control a phase of a second clock of the second plug-in unit, based on the phase-difference information, a second frame-pulse generator to generate the second frame-pulse-signal based on the second clock, and a second transmitter to transmit the second frame-pulse-signal to the first plug-in unit.
Encapsulation of Digital Communications Traffic for Transmission on an Optical Link
A method (10) of encapsulating digital communications traffic for transmission on an optical link, the method comprising: a. receiving an input digital communications signal having an input line code (12); b. performing clock and data recovery on the input digital communications signal to obtain input line coded digital communications traffic and a recovered clock signal (14); c. decoding the input digital communications traffic to obtain information bits and non-information bits (16); d. removing the non-information bits (18); e. adding service channel bits for monitoring or maintenance (20); f. assembling the service channel bits and information bits into frames (22); and g. line coding the assembled frames using an output line code to form an encapsulated digital communications signal for transmission on an optical link (24), wherein steps c. to g. are performed using the timing of the recovered clock signal. A communications network receiver configured to implement the method is also provided.
TRANSMISSION APPARATUS AND PLUG-IN UNIT
A transmission apparatus includes: a first plug-in unit including: a clock generator to generate a first clock, a first frame-pulse generator to generate a first frame-pulse-signal based on the first clock; a detector to detect a phase-difference between a first phase of the first frame-pulse-signal and a second phase of a second frame-pulse-signal transmitted from other plug-in unit, and generate phase-difference information based on the phase-difference, and a first transmitter to transmit a control-signal including the phase-difference information to the other plug-in unit; and a second plug-in unit being the other plug-in unit, including: a receiver to receive the control-signal, a controller to control a phase of a second clock of the second plug-in unit, based on the phase-difference information, a second frame-pulse generator to generate the second frame-pulse-signal based on the second clock, and a second transmitter to transmit the second frame-pulse-signal to the first plug-in unit.
TRANSMISSION APPARATUS
There is provided a transmission apparatus including: a shift register configured to generate a plurality of timing pulses indicating different timings, from a frame pulse synchronized with a frame signal; and a plurality of signal processors configured to sequentially process the frame signal based on timings indicated by one or more timing pulses among the plurality of timing pulses.
Clock generation with non-integer clock dividing ratio
A clock generator for generating a clock equivalent to a target clock which is an input clock divided by a non-integer ratio is disclosed. The clock generator comprises a clock divider configured to receive the input clock and divide the input clock with a reconfigurable dividing ratio; and a control circuit controlling operations of the clock divider to divide the input clock by a first dividing ratio to generate a first number of cycles of a first clock in a frame, and divide the input clock by a second dividing ratio to generate a second number of cycles of a second clock in the frame, wherein a difference between a period of the frame and a cumulative time of the first number of cycles of the first clock and the second number of cycles of the second clock is less than a threshold value.
Optical communication cross-connection devices and signal processing method thereof
Provided is an optical communication cross-connection device for exchanging an OTN signal through optical communications, including: a plurality of OTN signal processing units (OTNsp units) for asynchronously conducting OTN signal processing; and a space switch connected between the plurality of OTNsp units, for conducting bidirectional signal exchange for the OTN signal, in which a first and a second OTNsp units that conduct signal transmission among the plurality of OTNsp units subject the OTN signal to skew processing on one side and deskew processing corresponding to the skew processing on another side between the first and second OTNsp units or between a communicating end-side one of the first and second OTNsp units and a communicating end-side OTNsp unit of an optical communication cross-connection device of a communication counterpart destination for the optical communication cross-connection device, and share a clock for the signal transmission therebetween.
Systems and methods for synchronization of clock signals
A system may include a transmitting device. The transmitting device may include one or more terminals for receiving a data signal and a first clock signal. A first phase lock loop may lock a phase of an initial periodic signal with a phase of the first clock signal, the first phase lock loop including a divider to generate the initial periodic signal based on the first clock signal. A decimation module may sample the initial periodic signal at a decimated rate of a backplane clock, the backplane clock being asynchronous with a clock that generated the first clock signal. A transmitting data block interface may construct data blocks and provide the data blocks to a receiving device, each of one or more of the data blocks including a portion of the data signal and at least one sample of the initial periodic signal.