Systems and methods for implementing bi-directional synchronization propagation between first and second communication devices are provided. The devices are arranged in a loop-timing configuration. A method includes detecting, by the second communication device, a switching signal comprising an indication to switch a timing role of the second communication device and engaging, by the second communication device, in a synchronization handshake with the first communication device over a communication link based on the detection of the switching signal. Engaging in the synchronization handshake includes determining whether the first communication device is configured to support bi-directional synchronization propagation. The method includes switching the timing role of the second communication device based on the synchronization handshake.

A mapper physical layer device (PHY) is disclosed that performs a protocol conversion of an input data stream that is formatted according to a first wired communication protocol to provide an output data stream that is formatted according to a second wired communication protocol. The mapper PHY can be synchronized to a common reference clock or clocking source to ensure that data streams provided by multiple mapper PHYs are sufficiently aligned to satisfy frame timing alignment accuracy requirements of a wireless communication protocol.

A de-serializer, such as forming part of a SERDES, in which a point in time of receipt, on the serial data path, of receipt of a particular part of a data packet, such as an SOF, is determined from when that part is output on the parallel data path from knowledge of the clock controlling the parallel data path as well as which of the parallel lanes the part is output on.

Provided is a method for calculating a timestamp associated with a data packet before transcoding of the data packet. The method may include sampling a time of day (TOD) signal to provide a sampled TOD. A previously sampled TOD estimate may be retrieved. An internal TOD estimate may be determined based on the sampled TOD and the previously sampled TOD estimate. A timestamp may be determined based on the internal TOD estimate. A system and computer program product are also disclosed.

The present technology relates to a transmission apparatus, a transmission method, a reception apparatus, and a reception method that enable channel selection information and time information to be transmitted effectively.

A transmission apparatus acquires channel selection information for selecting a service and time information used for synchronizations on a transmission side and a reception side, generates, as a physical layer frame constituted of a preamble and a data portion, the physical layer frame in which specific information including at least one of the channel selection information and the time information is arranged at a head of the data portion right after the preamble, and transmits the physical layer frame as digital broadcast signals. The present technology is applicable to IP packet broadcasting, for example.

A network device includes a packet processor, a plurality of interface circuits, a phase-locked loop (PLL) circuit and a configuration controller. The interface circuits are configured to transmit and receive signals to/from other devices that are coupled to the network device. A master interface circuit among the interface circuits is configured to recover a network clock from a received signal. The PLL circuit is configured to generate an interface clock based on a system clock of the network device and a configuration of the PLL circuit and to provide the interface clock to the plurality of interface circuits to govern communication timings of the interface circuits. The configuration controller is configured to detect a difference of the interface clock relative to the recovered network clock, and to determine the configuration of the PLL circuit based on the difference to govern operation of the PLL circuit.

A rate adaptation system includes a barrel shift slot register and a rate adaptation register. The barrel shift slot register includes a plurality of slots with one of a valid read request or a dummy read request. A rate adaptation register is configured to sequentially cycle through the slots of the barrel shift register in response to a clock providing valid read requests to a FIFO buffer and to skip provision of valid read requests for clock cycles of the first clock associated with slots that include dummy read requests. The rate adaption register may also receive data blocks from the FIFO buffer and provide those data blocks to another FIFO buffer.

A semiconductor device includes a first timer that includes a first counter, a second timer that includes a second counter and a controller that includes a CPU in provision of a technology for efficiently diagnosing a fault of a timer that is built in the semiconductor device such as a microcontroller and so forth. The first timer performs time synchronization with the time of external equipment arranged outside the semiconductor device. The controller compares a count value of the first counter with a count value of the second counter and detects a malfunction of the second timer on the basis of a result of comparison.

A mobile communication device according to one embodiment includes a receiver, an imager, a detector, a determiner. The receiver configured to receive a frame including a first timing, a second timing, and first position information. The imager configured to capture the imaging target for a plurality of times. The detector configured to detect second position information, and third position information. The determiner determines whether or not the frame received by the receiver is a frame transmitted in tandem with an operation performed by the imaging target based on first to fourth timings. The corrector, when the determiner configured to determine that the frame received by the receiver is a frame transmitted in tandem with an operation performed by the imaging target, correct a timing of the clock based on the first to third position information and the first to fourth timings.

A system and a method of sampling an event signal using multiple clocking signals each provided in a separate candidate clock domain each of which also receives points in time from a master clock. From each candidate clock domain, clocked by the individual clocking signals, pairs of a received point in time and event signal value are fed to a master clock domain. In the master clock domain, the values of the event signal may be determined over time as a function of master clock time. This may be used for synchronizing operation in the master clock domain of e.g. packet time stamping with an overall time defined by the event signal. Using multiple clocking signals for the sampling, a much more precise sampling of the event signal is facilitated.