A user station for a bus system and a method for checking the correctness of a message, in which the user station includes a communication control unit for writing or reading at least one message for/from at least one further user station of the bus system, in which an exclusive, collision-free access by a user station to a bus line of the bus system is ensured at least intermittently, a checksum generator for generating a checksum for the message to detect bit errors in the message, and a configuration register for specifying the initialization value with which the checksum generator is to be preloaded to start the message, the initialization value being changeable as necessary even following a communication with the communication control unit.

A user station for a serial bus system. The user station includes a receiver for receiving a signal from a bus of the bus system, and a device for evaluating the reception signal that is output by the receiver. The receiver generates a digital reception signal from the signal received from the bus and to output the signal to the device at a terminal. The device evaluates the digital reception signal with regard to a predetermined communication protocol that establishes when a predetermined communication phase, which indicates a subsequent transfer of useful data in a message, begins and ends. The device reverses the data flow of the digital reception signal to the receiver at the terminal for a time period of at least one bit if the evaluation of the device shows that data at that time are being received from the bus in the predetermined communication phase.

A controller area network (CAN) node comprises an internal high differential bus line (CANH) and an internal low differential bus line (CANL). The CAN node further comprises a receiver (RXD) comparator coupled to both the internal CANH and the internal CANL that outputs an internal RXD signal. The CAN node further comprises an RXD dominant time out (DTO) circuit. The RXD DTO circuit includes: a) an RXD dominant transition detector coupled to an output of the RXD comparator; b) a timer triggered by the RXD dominant transition detector detecting a dominant RXD transition; c) an RXD dominant timer comparator that is coupled to an output of the timer which compares an output of the timer to a selected value; d) an internal RXD dominant signal is changed to an RXD DTO recessive signal after a selected time interval has lapsed and can include a fault output to signal this fault condition.

A CAN FD frame comprises one or more portions provided at a normal bit rate that includes an end-of-frame field consisting of a succession of at least seven recessive bits. A method for detecting the end-of-frame of a CAN FD frame in an input bit stream entails providing a recessive bit count; defining a stretched bit transmission time longer than the bit transmission time associated with the high data rate; stretching the bit transmission time of each dominant bit succeeding a recessive bit in the input bit stream to the stretched bit transmission time to generate a conditioned input bit stream; sampling the conditioned input bit stream at a bit counter rate to generate a sampled bit stream; resetting the recessive bit count in response to each dominant bit in the sampled bit stream; and incrementing the recessive bit count in response to each recessive bit in the sampled bit stream.

The disclosure relates to a method for serially transmitting frames from a transmitter to at least one receiver via a bus line and to a participant station for a bus system. In the method, stuff bits are integrated into the frame by the transmitter dependent on the values of multiple previous bits in order to generate additional signals edges. The transmitter of the frame counts the stuff bits which are integrated depending on the value of multiple previous bits, and information on the number of counted stuff bits is transmitted in the transmitted frames.

An error detection test device for a subscriber station of a serial bus system. The error detection test device has an evaluation module for evaluating which bit of a signal must be interrupted so that the receivers of the resulting signal in which the at least one bit is interrupted can check the function of an error detection mechanism, the signal being processed by a protocol control unit while the subscriber station is in operation in order to be able to be transmitted as a frame onto a bus of the bus system or, after a frame has been received from the bus, to decode the signal from the frame, and an output terminal for outputting a switching signal to the protocol control unit to interrupt the at least one bit. The evaluation module generates the switching signal based on the at least one bit evaluated by the evaluation module.

A device and method for a serial bus system. The device has a transmit signal analysis module for counting edges of a transmit signal to be transmitted on a bus of the bus system; a receive signal analysis module for counting edges of a receive signal generated from a signal transmitted on the bus because of the transmit signal; and an evaluation module for evaluating the difference that results from a comparison of the edges counted by the transmit signal analysis module and the edges counted by the receive signal analysis module. If the signal propagation time on the bus is greater than the bit time of the receive signal, the evaluation module signals whether the amount of the difference is less than or equal to a predefined value or whether the amount of the difference is greater than the predefined value, the predefined value being greater than zero.

Embodiments relate to including information in a data packet transmitted by a transmitting integrated circuit (e.g., SOC) to account for a time delay associated with an unsuccessful arbitration attempt to send the data packet over a multi-drop bus. The unsuccessful arbitration attempt by the integrated circuit may delay the transmission of the data packet until the multi-drop bus becomes available for the integrated circuit to send the data packet. The data packet includes a data field to include time delay information caused by the unsuccessful arbitration attempt. A receiving integrated circuit may determine the time that the data packet would have been sent out from the transmitting integrated circuit absent the unsuccessful arbitration attempt based on the delay information. Embodiments also relate to a synchronization generator circuit in an integrated circuit that generates timing signals indicating times at which periodic events occur at another integrated circuit.

A user station for a serial bus system and a method for transmitting a message in a serial bus system. The user station includes a communication control device for transmitting messages to a bus of the bus system and/or for receiving messages from the bus of the bus system, and a bit rate switchover unit for switching over a bit rate of the messages from a first bit rate in a first communication phase to a second bit rate for a second communication phase. The bit rate switching unit is designed to switch the bit rate from the first bit rate over to the second bit rate, due to an edge of a predetermined bit sequence that includes one bit of the first communication phase and one bit of the second communication phase.

The transmission of a recessive bit in a CAN message from a transmitting electronic control unit (ECU) is detected, over a controller area network. A dominant pulse is injected onto the network after a delay time into the detected recessive bit. Behavior of the transmitting ECU is detected, and a sample point for the transmitting ECU is characterized based upon the detected ECU behavior. An action signal is generated based upon the characterized sample point.