A method and related apparatus for outputting an analog signal are disclosed. A plurality of transmit levels corresponding to respective predetermined equalization levels is provided. A stream of digital signals carrying data is provided. A transmit level from among the plurality of transmit levels based on the digital signals carrying data is selected. The selected transmit level is received, the selected transmit level is converted to an analog signal of the selected transmit level, and the analog signal of the selected transmit level is output over a signal interface.

A transmitter of the present disclosure includes: an output terminal; a driver that performs transition of a voltage of the output terminal among a plurality of voltages; and a controller that controls the driver to cause transition start timing in one voltage transition in voltage transition among the plurality of voltages to be later than transition start timing in another voltage transition.

A transmitter of the present disclosure includes: an output terminal; a driver that performs transition of a voltage of the output terminal among a plurality of voltages; and a controller that controls the driver to cause transition start timing in one voltage transition in voltage transition among the plurality of voltages to be later than transition start timing in another voltage transition.

A transmitter for providing channel equalization that includes a first driver and second driver having a high pass filter. The first driver generates a first output signal representing a digital input signal. The second driver generates a second output signal representing a high pass filtered version of the digital input signal. The first and second output signals are summed to provide a third output signal that is channel equalized for transmission over a channel.

There is provided a transmission device including a transmission unit that has a function of transmitting a transmission signal with a reduced influence of reflection noise in transmission data after data transition on the basis of the transmission data. The transmission device is connected to a transmission line. Also provided is a reception device connected to the transmission line. The reception device receives data transmitted from the transmission device.

The present invention provides a semiconductor device realizing suppression of increase in consumption power. A semiconductor device has a signal line, a reception buffer circuit which is coupled to an end of the signal line and to which a signal is supplied from the signal line, and a delay element which is wired-OR coupled to an end of the signal line and shapes a waveform of a signal at the end of the signal line.

A memory interface may include a transmitter that generates multi-level signals. The transmitter may employ channel equalization to improve the quality and robustness of the multi-level signals. The channel equalization may be controlled independently from the drive strength of the multi-level signals. For example, a first control signal may control the de-emphasis or pre-emphasis applied to a multi-level signal and a second control signal may control the drive strength of the multi-level signal. The first control signal may control a channel equalization driver circuit and the second control signal may control a driver circuit.

A system includes the transmitter that transmits a first adjustment signal obtained based on a first parameter, detects, based on an output potential of the transmitter, a second parameter that is among values settable to the first parameter and sets the second parameter and the receiver that receives the first adjustment signal from the transmitter and acquire a second adjustment signal by adjusting the first adjustment signal based on a third parameter, sets the third parameter, counts the number of errors of the second adjustment signal based on a difference between the second adjustment signal and the test pattern, determines, based on the number of errors of the second adjustment signal, the second parameter to be set in the transmitter and controls the connection of the terminal resistor to the input terminal based on the second parameter.

A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data.

A memory interface may include a transmitter that generates multi-level signals. The transmitter may employ channel equalization to improve the quality and robustness of the multi-level signals. The channel equalization may be controlled independently from the drive strength of the multi-level signals. For example, a first control signal may control the de-emphasis or pre-emphasis applied to a multi-level signal and a second control signal may control the drive strength of the multi-level signal. The first control signal may control a channel equalization driver circuit and the second control signal may control a driver circuit.