A receiver is configured to capture a plurality of linearly distorted OFDM symbols transmitted over a signal path. The receiver forms the captured OFDM symbols into an overlapped compound data block that includes payload data and at least one pseudo-extension, processes the overlapped compound block with circular convolution in the time domain using an inverse channel response, or frequency domain equalization, to produce an equalized compound block, and discards end portions of the equalized block to produce a narrow equalized block. The end portion corresponds with the pseudo-extension, and the narrow block corresponds with the payload data. The receiver cascades multiple narrow equalized blocks to form a de-ghosted signal stream of OFDM symbols. The OFDM symbols may be OFDM or OFDMA, and may or may not include a cyclic prefix, which will have a different length from the pseudo-extension.

A receiving link device includes a receiver (RX) to receive a data signal from a transmitting link device, the receiver including an equalizer to detect RX tap values and a processing device coupled to the receiver, the processing device to perform operations including: programming the receiver with information related to target RX tap values that are associated RX pre-cursors or RX post-cursors; detecting, using the equalizer, that an RX pre-cursor value is greater or less than a target RX tap value; generating, based on the detecting, a tap message including an up or a down command to decrease or increase a corresponding transmitter (TX) pre-cursor value of the transmitting link device; and causing the tap message to be provided to a local transmitter to be transmitted to a remote receiver of the transmitting link device, which causes the transmitting link device to adjust the corresponding TX pre-cursor value.

Some examples described herein provide an integrated circuit comprising an auxiliary clock and data recovery (CDR) circuitry. The CDR circuitry is configured to oversample an incoming data signal and generate a locked clock signal. The auxiliary CDR circuitry may comprise a phase-locked loop (PLL) configured to receive the incoming data signal and generate the locked clock signal. The PLL may comprise a phase detector (PD) configured to receive the incoming data signal and capture a number of samples of the incoming data signal in response to a number of adjacent clock signals and minimum data transition thresholds implemented by an intersymbol interference (ISI) filter, the minimum data transition thresholds identifying minimum data transitions in the incoming data signal.

A receiving link device includes a receiver (RX) to receive a data signal from a transmitting link device, the receiver including an equalizer to detect RX tap values and a processing device coupled to the receiver, the processing device to perform operations including: programming the receiver with information related to target RX tap values that are associated RX pre-cursors or RX post-cursors; detecting, using the equalizer, that an RX pre-cursor value is greater or less than a target RX tap value; generating, based on the detecting, a tap message including an up or a down command to decrease or increase a corresponding transmitter (TX) pre-cursor value of the transmitting link device; and causing the tap message to be provided to a local transmitter to be transmitted to a remote receiver of the transmitting link device, which causes the transmitting link device to adjust the corresponding TX pre-cursor value.

System and method of timing recovery for recovering a clock signal with reduced interaction between an adaptive channel estimator and the overall timing loop for correcting clock phase. The channel response estimation in the timing recovery loop is dynamically adapted to the current channel response that varies over time. The channel estimator includes compensation logic operable to detect and compensate a correction of clock phase ascribed to the channel estimator. The compensation logic can calculate the offset between a center of filter (COF) value and a COF nominal value, the offset indicative of the amount and direction of clock phase correction contributed by the channel estimator. Based on the offset, the compensation logic adjusts the estimates channel response by adjusting the tap weights of the channel estimator to correct the offset, thereby compensating the clock phase correction.

A receiver and method for compensating for linear impairments at a receiver including receiving an Rx signal including an asymmetric response of a satellite filter; pre-equalizing the Rx signal with a coefficient; and demodulating, after the pre-equalizing, the Rx signal.

An integrated circuit may include a receiver configured to receive a first data signal based on an m.sup.th (where m is an integer of 1 or more) transmitter preset setting among a plurality of transmitter preset settings through an external link, and equalize and sample the first data signal; a receiver setting table including a plurality of combinations including values of a plurality of parameters related to the receiver; and a receiver control circuit configured to sequentially select the plurality of combinations with reference to the receiver setting table and set the plurality of parameters with the selected combinations.

A die-to-die data transmitter is disclosed with a pull-up one-shot circuit and a pull-down one-shot circuit, each forming a delay circuit that determines a variable preemphasis period.

An equalizer circuit includes: a pair of input terminals: a differential amplification circuit outputs, to a pair of output terminals, first signals obtained by amplifying a difference in levels of input signals supplied to the pair of input terminals; and a differential differentiation amplification circuit that outputs, to the pair of output terminals, second signals obtained by amplifying a time-varying change in the difference in the levels of the input signals supplied to the pair of input terminals.

An integrated circuit is disclosed and includes an Ethernet physical layer (PHY) with a plurality of communication channels. The communication channels coupled to a corresponding plurality of terminals. The integrated circuit further includes a plurality of electrical isolation circuits and a compensation circuit. At least one of the plurality of electrical isolation circuits is coupled to a corresponding one of the plurality of communication channels and electrically isolates the PHY from a corresponding one of the plurality of terminals. The compensation circuit is configured to compensate for at least one of baseline wander and parameter drift associated with at least one of the plurality of isolation circuits. The PHY and the plurality of isolation circuits are integrated on a single substrate.