The present invention discloses a method for the design of complex-valued channel equalizer of digital communication systems, including: constructing a channel equalizer by using a complex-valued neural network; collecting the output signal y(n)=[y(n), y(n−1), . . . , y(n−m+1)].sup.T of the nonlinear channel of the underlying digital communication system as the input of complex-valued neural network and s(n−τ) as the desired output, and taking the mean squared error as the loss function for the training of complex-valued neural network, which is optimized by the proposed adaptive complex-valued L-BFGS algorithm, and finally using it to implement the design of channel equalizer for digital communication systems. The present invention proposes the use of a multi-layer feedforward complex-valued neural network to construct complex-valued channel equalizer. A new adaptive complex-valued L-BFGS algorithm is proposed for efficient training of complex-valued neural network, which is eventually applied to facilitate the design of the channel equalizer for digital communication systems.

A decision feedback equalizer including: a first input latch configured to generate a first output signal from first data received by the first input latch, wherein the first input latch includes: a first sub-circuit configured to receive the first data and a reference voltage, compare the first data and the reference voltage, and generate first internal signals having different transition timings according to a result of the comparison between the first data and the reference voltage; and a second sub-circuit configured to receive, as first feedback, a second output signal, which corresponds to second data received by the first latch earlier than the first data, and generate the first output signal, which compensates for a difference between the transition timings of the first internal signals, based on the first feedback.

Embodiments herein disclose a receiver for performing adaptive equalization of data samples, wherein the receiver comprises an adaptation circuitry and an equalizer coupled to the adaptive circuitry. The adaptive circuitry is configured to estimate a pulse response of a channel, on receiving at least one data sample over the channel, wherein the pulse response of the channel identifies an intersymbol interference (ISI) present on the received at least one data sample. The equalizer is configured to perform equalization of the received at least one data sample by cancelling the identified ISI on the received at least one data sample

A detection method for a MIMO system receiver in which a linear detection is carried out in order to provide an equalised vector. This equalised vector is represented in a reduced basis obtained from the reduction of the channel matrix. It undergoes an iterative noise cancellation process in the representation according to the reduced basis. Upon each iteration, a search is carried out for the component of the equalised vector in the reduced basis located the furthest from an area unperturbed by noise surrounding the product constellation with a tolerance margin, and the point representative of the equalised vector of this area by subtracting therefrom a noise vector in the direction of this component, the module whereof is equal to a fraction of the tolerance margin. The iterative cancellation converges when the equalised vector belongs to the area unperturbed by noise.

A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

A continuous time linear equalization (CTLE) circuit is disclosed. The CTLE circuit includes a passive CTLE circuit and an active CTLE circuit. The active CTLE circuit includes a differential transistor pair and the output of the passive CTLE is configured to drive gates or bases of the differential transistor pair.

A high bandwidth continuous time linear equalization (HBCTLE) circuit is disclosed. The HBCTLE circuit includes a continuous time linear equalization (CTLE) circuit and a gain circuit coupled with an output of the CTLE circuit. A feedback circuit is coupled between the output of the CTLE circuit and an output of the gain circuit.

A continuous time linear equalization (CTLE) circuit is disclosed. The CTLE circuit includes a passive CTLE circuit and an active CTLE circuit. The active CTLE circuit includes a differential transistor pair and the output of the passive CTLE is configured to drive gates or bases of the differential transistor pair.

A continuous time linear equalizer (CTLE) is disclosed. The CTLE may include a first cell configured to buffer and invert an input signal and generate a first intermediate signal, a second cell configured to buffer and invert the input signal and generate a second intermediate signal, and a first frequency section configured to selectively buffer and invert a first range of frequencies of the second intermediate signal. The first frequency section may include a first tunable resistor configured to provide a first resistance and a third cell coupled to the first tunable resistor configured to generate a third intermediate signal based on the first resistance.

Adaptive equalizer circuitry including both a continuous time equalizer (CTE) and a discrete time equalizer (DTE) and a method of jointly adapting the CTE and DTE in lane adaptation. Jointly adaptation of the CTE and DTE is performed by adapting the DTE at each of a plurality of filter characteristic settings of the CTE and determining a figure of merit for signals filtered by the CTE and DTE at that condition. Adaptation of the DTE may be performed by dynamically adjusting a convergence coefficient based on a history of error gradients. After a figure of merit is determined for each of the plurality of CTE filter characteristics, a CTE filter characteristic setting is then selected based on those figure of merit values, for example at a CTE setting near a midpoint of an acceptable region of figure of merit values.