A circuit includes an AGC adaptation circuit configured to receive a first signal generated based on an AGC output signal from an AGC circuit. The AGC circuit applies an AGC gain to an AGC input signal to generate the AGC output signal. The AGC adaptation circuit determines an observed value of the first signal, and determines a AGC adaptation step size based on the observed value and a predetermined target value associated with the first signal. The AGC adaptation circuit provides a second signal to adjust the AGC gain of the AGC circuit using the AGC adaptation step size.

A random access memory (RAM) including a deserializer is disclosed. The RAM further comprises a continuous-time linear equalizer (CTLE) including a first input terminal that receives an input signal for the RAM and a first output terminal communicatively connected to the deserializer, the CTLE configured to perform a channel gain compensation on the input signal received by the first input terminal and to transmit the compensated input signal to the deserializer. The RAM may further comprise a decision feedback equalizer (DFE) including a second input terminal communicatively connected to the CTLE and a second output terminal communicatively connected to the deserializer, the DFE configured to reduce an inter-symbol interference (ISI) of the input signal.

A driving adjustment circuit and an electronic device are provided. The driving adjustment circuit includes a first NOT gate module, second NOT gate module and third NOT gate module sequentially connected. An input terminal of the first NOT gate module and an output terminal of the third NOT gate module are connected to a signal terminal. The first NOT gate module acquires a to-be-driven signal from the signal terminal and perform a NOT operation on the to-be-driven signal to obtain a first adjustment signal. The second NOT gate module receives the first adjustment signal and performing the NOT operation on the first adjustment signal to obtain a second adjustment signal, when the driving adjustment circuit is in an ON state. The third NOT gate module receives the second adjustment signal and perform voltage adjustment processing on the to-be-driven signal at the signal terminal according to the second adjustment signal.

Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.

The system and method for adaptively obtaining coefficients of an inverse model for both equalization and pre-distortion for a multi-channel and reconfigurable RF system. The system preforms real-time learning and adaption and does not require training sets. In some cases, the system learns new coefficients across time and transient changes in performance.

Multipath filters are provided herein. In certain configurations, a multipath filter includes multiple filter paths or circuit branches that are electrically connected in parallel with one another between an input terminal and an output terminal. The input terminal receives an input signal, and each filter circuit branch includes a double-in double-switched (DIDS) downconverter that downconverts the input signal with two different clock signal phases to generate a downconverted signal. Each filter circuit branch further includes a filter network that generates a filtered signal by filtering the downconverted signal and an upconverter that upconverts the filtered signal to generate a branch output signal. Additionally, the branch output signals from the filter circuit branches are combined to generate an output signal at the output terminal.

Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.

A receiver is configured to capture a plurality of linearly distorted OFDM symbols transmitted over a signal path. The receiver forms the captured OFDM symbols into an overlapped compound data block that includes payload data and at least one pseudo-extension, processes the overlapped compound block with circular convolution in the time domain using an inverse channel response, or frequency domain equalization, to produce an equalized compound block, and discards end portions of the equalized block to produce a narrow equalized block. The end portion corresponds with the pseudo-extension, and the narrow block corresponds with the payload data. The receiver cascades multiple narrow equalized blocks to form a de-ghosted signal stream of OFDM symbols. The OFDM symbols may be OFDM or OFDMA, and may or may not include a cyclic prefix, which will have a different length from the pseudo-extension.

Methods and apparatus for implementing adaptive equalization channel extension retimer link-up in high-speed serial links. Under aspects of the proposed methodology, the retimer device intervenes with the adaptive equalization training, training both ends of the link individually between the two end points, and once both of the retimer's receivers are trained, it propagates the receiver readiness indication through from one end point to the other. This allows all sections of the link to train at the same time, and for all devices to transition to data mode at the same time, once all channels have been adapted to and trained. This methodology also applies to cascaded retimer device configurations, where multiple retimers are being used to extend the channel even further.

A receiver is configured to capture a plurality of linearly distorted OFDM symbols transmitted over a signal path. The receiver forms the captured OFDM symbols into an overlapped compound data block that includes payload data and at least one pseudo-extension, processes the overlapped compound block with circular convolution in the time domain using an inverse channel response, or frequency domain equalization, to produce an equalized compound block, and discards end portions of the equalized block to produce a narrow equalized block. The end portion corresponds with the pseudo-extension, and the narrow block corresponds with the payload data. The receiver cascades multiple narrow equalized blocks to form a de-ghosted signal stream of OFDM symbols. The OFDM symbols may be OFDM or OFDMA, and may or may not include a cyclic prefix, which will have a different length from the pseudo-extension.