The technology relates to bandwidth constrained communication systems with neural network based detection. In some embodiments, a bandwidth constrained equalized transport (BCET) communication system comprises: a transmitter comprising an error control code encoder, a pulse-shaping filter, and a first interleaver; a communication channel; and a receiver comprising a neural network processing block that processes a received signal. The error control code encoder can append redundant information onto the signal. The pulse-shaping filter can intentionally introduce memory into the signal in the form of inter-symbol interference. The first interleaver can change a temporal order of the symbols in the signal. The error control code encoder can be a low-density parity-check (LDPC) error control code encoder. The neural network can be trained with positive mappings between transmitted and decoded training signals, or negative mappings between training signals and a null space of an LDPC generation matrix.

A Viterbi Equalizer having a limited number of stages is disclosed. In some embodiments, the Viterbi Equalizer may have only four stages. The Viterbi Equalizer produces soft decisions, which comprise a final decision and reliability information related to that final decision. The Viterbi Equalizer is able to provide reliability information even if all paths do not converge on the final decision at the last stage. The reliability information is calculated based on if and when the paths in the trellis converge on a final decision. This reliability information can be used downstream, such as by another Viterbi Algorithm block to perform forward error correction. The use of soft decision provides gains of up to several dB in performance. Additionally, the Viterbi Equalizer is low cost and readily implemented in hardware or software.

The present disclosure provides techniques for bandwidth constrained communication systems with frequency domain information processing. A bandwidth constrained equalized transport (BCET) communication system can include a transmitter, a communication channel, and a receiver. The transmitter can include a pulse-shaping filter that intentionally introduces memory into a signal in the form of inter-symbol interference, an error control code (ECC) encoder, a multidimensional fast Fourier transform (FFT) processing block and a multidimensional inverse FFT processing block that process the signal in the frequency domain, and a first interleaver. The receiver can include an information-retrieving equalizer, a deinterleaver with an ECC decoder, and a second interleaver joined in an iterative ECC decoding loop. The communication system can be bandwidth constrained, and the signal can comprise an information rate that is higher than that of a communication system without intentional introduction of the memory at the transmitter.

The present disclosure provides techniques for bandwidth constrained communication systems with frequency domain information processing. A bandwidth constrained equalized transport (BCET) communication system can include a transmitter, a communication channel, and a receiver. The transmitter can include a pulse-shaping filter that intentionally introduces memory into a signal in the form of inter-symbol interference, an error control code (ECC) encoder, a multidimensional fast Fourier transform (FFT) processing block and a multidimensional inverse FFT processing block that process the signal in the frequency domain, and a first interleaver. The receiver can include an information-retrieving equalizer, a deinterleaver with an ECC decoder, and a second interleaver joined in an iterative ECC decoding loop. The communication system can be bandwidth constrained, and the signal can comprise an information rate that is higher than that of a communication system without intentional introduction of the memory at the transmitter.

The present disclosure provides a baseband chip and a baseband chip management system. The baseband chip comprises an application processor, an interface module, a channel encoder, a digital signal processor, and a modem module group. The modem module group includes an integrated modem module and a power module. The integrated modem module comprises at least two modems. The application processor is connected to the interface module, the channel encoder, the digital signal processor, and the power module respectively. The baseband chip management system comprises a baseband chip and a radio frequency integrated system. The radio frequency integrated system comprises at least two radio frequency module systems.

This application discloses a decoding method for an OvXDM system, including: generating an augmented matrix B related to a received symbol information sequence; performing singular decomposition on the augmented matrix B; and performing decoding by using a total least square method, to obtain a decoded output information sequence. This application further discloses an OvXDM system. In a specific implementation of this application, decoding is performed by using the total least square method.

A symbol-determining device according to an embodiment includes: a transmission line shortening unit that multiplies each symbol value of a symbol array that is part of an input signal by a tap gain of a linear digital filter and outputs a symbol array representing a sum of values acquired through the multiplication; a transmission line estimating unit that estimates a transfer function of a transmission line using an adaptive nonlinear digital filter on the basis of a symbol array representing a state of the transmission line; an addition comparison processing unit that calculates a minimum value of a distance function in a Viterbi algorithm on the basis of a metric that is calculated on the basis of the output of the transmission line shortening unit and the transfer function; and a path tracing-back determination unit that performs symbol determination by tracing back a trellis path in the Viterbi algorithm on the basis of the minimum value of the distance function.

There is provided a decoder for decoding a data signal received through a transmission channel in a communication system, the decoder (310) comprising a symbol estimation unit (311) configured to determine estimated symbols representative of the transmitted symbols carried by the received signal, the estimated symbols being determined from nodes of a decoding tree based on a weight metric associated with each of the node. The decoder further comprises a termination alarm monitoring unit (312) for monitoring a termination alarm depending on the current decoding computation complexity, the termination alarm being associated with a metric parameter, the symbol estimation unit being configured to reduce the weight metric of each node of the decoding tree by a quantity corresponding to a function of the metric parameter associated with the termination alarm, in response to the triggering of the termination alarm.

This application provides an error correction method, relates to the field of communications technologies, so as to reduce a bit error rate of a DFE and improve equalization performance. The method includes: obtaining a decision signal of a decision feedback equalizer DFE; obtaining at least one of an input signal, an equalized output signal, and a difference of the DFE, where the difference is a difference between a level value of the decision signal and a level value of the equalized output signal; determining a symbol location of an end of burst error of the decision signal based on detection of at least one of the decision signal, the equalized output signal, and the difference; and when the symbol location is detected, performing error correction on the decision signal based on the at least one of the input signal, the equalized output signal, and the difference.

A signal receiving circuit may include a receiving equalizer and a sequence estimator. The receiving equalizer may be configured to compensate an inter-symbol interference in a signal from an external to output an equalization data, based on a receiving signal from an outside. The sequence estimator may be configured to determine a termination symbol, based on the equalization data, to perform a decoding on the receiving signal, based on the determined termination symbol, and to output the decoded receiving signal as a sequence data.