A baseband system includes: an estimation and compensation circuit estimating frequency-independent non-ideal effects based on an original IQ signal pair, and compensating the original IQ signal pair based on a result of the estimation to obtain a compensated IQ signal pair; a channel estimation and equalization circuit performing channel estimation and equalization based on the compensated IQ signal pair to obtain an equalized IQ signal pair; and a tracking and compensation circuit obtaining a result of tracking of residual quantities of the aforesaid non-ideal effects based on the equalized IQ signal pair, and compensating the equalized IQ signal pair based on the result of the tracking to obtain an output IQ signal pair.

A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

A concurrent multi-band linearized transmitter (CMLT) has a concurrent d a multi-band predistortion block (CDMPB) and a concurrent multi-band transmitter (CMT) connected to the CDMPB, The CDMPB can have a plurality of digital baseband signal predistorter blocks (DBSPBs), an analyzing and modeling (A&M) stage, and a signal observation feedback loop. Each DBSPB can have a plurality of inputs, each corresponding to a single frequency band of the multi-band input signal, and its output corresponding to a single frequency band; each output connect corresponding to an input of the CMLT. The A&M stage can have a plurality of outputs connected to and updating the parameters of the DBSPBs, and a plurality of inputs connected to either both outputs of the signal observation loop or the output of the subsampling loop and to outputs of the DBSPBs. The A&M stage can perform signals' time alignment, reconstruction of signals and compute parameters of DBSPBs.

A baseband system includes: an estimation and compensation circuit estimating frequency-independent non-ideal effects based on an original IQ signal pair, and compensating the original IQ signal pair based on a result of the estimation to obtain a compensated IQ signal pair; a channel estimation and equalization circuit performing channel estimation and equalization based on the compensated IQ signal pair to obtain an equalized IQ signal pair; and a tracking and compensation circuit obtaining a result of tracking of residual quantities of the aforesaid non-ideal effects based on the equalized IQ signal pair, and compensating the equalized IQ signal pair based on the result of the tracking to obtain an output IQ signal pair.

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

The disclosed systems, structures, and methods are directed to a superposition based transceiver. The configurations presented herein employ a plurality of encoders configured to encode a plurality of input digital data streams, wherein each of the plurality of input digital data streams operates at different data rates, a plurality of modulators configured to modulate the plurality of encoded digital data input streams. In addition, a plurality of transmitter filters configured to perform up-sampling and filtering of the plurality of modulated digital data streams, and a signal mixer configured to combine the plurality of up-sampled and filtered digital data streams into a single aggregate digital data stream in a manner such that the single aggregate digital data stream contains spectral characteristics that substantially conform to both a central area and a skirt area of a unified spectral emission mask, as specified by European Telecommunications Standards Institute (ETSI).

Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

A method and apparatus for providing feedback for cancellation of signal impairment in a plurality of separate transmit paths of a transmitter are disclosed. According to one aspect, a method includes receiving a plurality of outbound signals transmitted to the antenna array, the received outbound signals having traversed separate transmit paths of the transmitter. The method also includes converting the plurality of received outbound signals to a corresponding plurality of parallel baseband signals. The corresponding plurality of parallel baseband signals are serialized into a serial feedback signal.

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.