The present application relates to a baseband communications transceiver and a method of operating the baseband communications transceiver. The transceiver comprises an analog front end transmitter section, AFE TX, with a digital to analog converter, DAC, and a transmission, TX, driver; an analog front end receiver section, AFE RX, with an analog-to-digital converter, ADC; at least one equalizer arranged downstream of the AFE RX and implemented on the basis of an adaptive filter; at least one loss encode and a channel monitoring block. The at least one loss encode is configured to determine loss value data indicative of a signal loss on the communication channel based on filter coefficients of the adaptive filter. The channel monitoring block is configured to determine an amplitude control signal, which is provided to control the amplitude of analog signals generated by the TX driver of the AFE TX.

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

Methods, systems are provided for reconfiguring the position of a first tap in a descrambler circuit LFSR after the LFSR has been trained and synchronized with a corresponding scrambler circuit LFSR. A data path from the second tap position to the descrambler output by-passes logic elements located in the data path from the first tap to the descrambler output, thereby reducing delay in the descrambler circuit after the reconfiguration (i.e., the lock-shift operation). The tap position change may be communicated by a mode manager to a corresponding scrambler circuit, for applying a matching reconfiguration in the scrambler circuit, either directly via an I/O line or indirectly. The indirect route includes in-band transmissions between two ICs with two sets of self-synchronizing scrambler/descrambler pairs, and is based on monitored receiver LFSR output signals that indicate when a scrambler/descrambler pair is synchronized or whether the output of a descrambler circuit comprises descrambled data.

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

A test set system and related method are provided comprise a first direct digital synthesizer (DDS) having a balanced output configured to produce a first signal, and a second DDS having a balanced output signal configured to produce a second signal that differs from the first signal. The test set system also comprises a fully differential amplifier (FDA) having a balanced input that is connected to the balanced output of the first DDS and the balanced output of the second DDS, and a balanced output at which a combination of the first signal and the second signal is provided that suppresses even-order intermodulation products.

A system including filter circuits, a least mean square (LMS) engine, and a gain controller. A first filter circuit includes first taps that receive first coefficients. The first filter circuit filters a digital signal to generate a first filtered signal. One of the first coefficients is constrained. The LMS engine, based on a first input signal and a LMS algorithm, generates the first coefficients. A second filter circuit includes second taps that receive second coefficients. The second filter circuit filters the first filtered signal to generate a second filtered signal. The gain controller adjusts a gain of the digital signal based on a second input signal. The second filter circuit introduces: a difference in gain between outputs of the first and second filter circuits to adjust amplitudes of the first and second input signals; and a sampling phase offset between the outputs of the first and second filter circuits.

The present application relates to a baseband communications transceiver and a method of operating the baseband communications transceiver. The transceiver comprises an analog front end transmitter section, AFE TX, with a digital to analog converter, DAC, and a transmission, TX, driver; an analog front end receiver section, AFE RX, with an analog-to-digital converter, ADC; at least one equalizer arranged downstream of the AFE RX and implemented on the basis of an adaptive filter; at least one loss encode and a channel monitoring block. The at least one loss encode is configured to determine loss value data indicative of a signal loss on the communication channel based on filter coefficients of the adaptive filter. The channel monitoring block is configured to determine an amplitude control signal, which is provided to control the amplitude of analog signals generated by the TX driver of the AFE TX.

A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

An improved receiver design implements a method for modeling users in SIC turbo loop multiuser detection architectures that reduces the number of implementation cycles, and thereby reduces the computational overhead associated with computing the inverse of the received signal covariance matrix, by efficiently reusing components of a QR decomposition. By reusing some of the computational results from the previous turbo loop's equalizer calculation, the disclosed receiver significantly reduces the computational burden of updating the linear equalizer on each turbo loop. Depending on the embodiment, this reduction can be accomplished in at least two different ways, depending on the dimensionality and other aspects of the implementation.