Provided is an adaptive equalization processing circuit with which an adaptive equalization process converges in a stable manner without reducing the transmission efficiency. This adaptive equalization processing circuit is characterized by being equipped with: a demodulation means that demodulates a received signal, and generates and outputs a training signal; an adaptive equalization processing means that uses a tap coefficient (generated using the received signal or the training signal) to perform an adaptive equalization process for removing waveform distortion in the received signal, and then outputs an equalization output signal; and a selection means that selects the training signal when the adaptive equalization processing means is in a non-convergent state, and inputs the training signal to the adaptive equalization processing means.

An apparatus for controlling a feedback loop includes a digital finite impulse response filter configured to equalize digital samples to yield equalized data, a data detector circuit configured to detect values of the equalized data to yield detected data, a pattern detection circuit configured to detect at least one pattern in the detected data, an expected value comparison circuit configured to compare the digital samples corresponding to the at least one pattern with an expected value, and a feedback loop adaptation circuit configured to control a feedback loop based in part on whether the at least one pattern is detected by the pattern detection circuit and on an output of the expected value comparison circuit.

An apparatus for controlling a feedback loop includes a digital finite impulse response filter configured to equalize digital samples to yield equalized data, a data detector circuit configured to detect values of the equalized data to yield detected data, a pattern detection circuit configured to detect at least one pattern in the detected data, an expected value comparison circuit configured to compare the digital samples corresponding to the at least one pattern with an expected value, and a feedback loop adaptation circuit configured to control a feedback loop based in part on whether the at least one pattern is detected by the pattern detection circuit and on an output of the expected value comparison circuit.