The proposed communication protocol enables both asymmetrical and symmetrical communication using TDD based allocation system, while having Ethernet PHY compatibility for interface with other systems. Ethernet physical layer device is configured to process data from a MAC to a desired line rate and is configured with a a XGMII interface configured to transport data from the MAC. An encoder is configured to perform encoding on the data received over the XGMII interface to create encoded data. A burst mapper is configured to append OAM or reserved bit allocation to the encoded data to create mapped data and a PCS device configured process the mapped data to data burst that include a header and one or phy blocks of data.

A device includes a first interface to receive a signal from a first communication link, wherein the receive signal includes out-of-band (OOB) information. A detector coupled to the first interface detects the OOB information. An encoder coupled to the detector encodes the OOB information into one or more symbols (e.g., control characters). A second interface is coupled to the encoder and a second communication link (e.g., a serial transport path). The second interface transmits the symbols on the second communication link. The device also includes mechanisms for preventing false presence detection of terminating devices.

Some embodiments include apparatuses and methods having a component to change a value of a bit among a number of M bits of information when the M bits have the same value and when M exceeds a selected value. At least one of such embodiments can include a transmitting component to provide the information to a connection. At least one of such embodiments can include a receiving component to receive the information from the connection. In at least one of such embodiments, the selected value can include a maximum number of consecutive bits having the same value that such a receiving component can be configured to receive. Other embodiments including additional apparatuses and methods are described.

Implementations described herein include surgical helmet assemblies that have a helmet enclosure shaped to encircle a head of a user. The helmet enclosure retains a fan and includes a brow bar portion at a front of the helmet enclosure that is shaped to extend along a brow or a forehead of the user and having a light positioned therein. The helmet enclosure also includes a stabilizer extending downward from the helmet enclosure in front of the ears of a user, a face shield that is transparent and coupleable to at least the brow bar portion, a headband shaped to extend across an occiput region of the user's head, and a surgical garment for covering at least the head and shoulders of a user in use. The brow bar portion includes vents disposed therein to direct airflow pushed through the helmet enclosure from the fan onto the user. The face shield is coupleable to the helmet enclosure by one or more of a hook and loop fastener on the helmet enclosure or the stabilizer and a post protruding from the brow bar portion.

The disclosure relates to a coding module for an Ethernet transceiver. The coding module may include circuitry configured to: receive data-signaling representative of one or more data words; encode the data-signaling into one or more DC-balanced words each having a DC-balanced-word-length; provide a prepended-word for a first transmission, where a length of the prepended-word is at least as long as the DC-balanced-word-length; and provide the one or more DC-balanced words for a second transmission, where the second transmission is subsequent to the first transmission. The coding module may include circuitry configured to: receive a prepended-word and provide a logic-high signal to an Energy Detect terminal; receive one or more DC-balanced words each having a DC-balanced-word-length; remove a DC-balanced coding from the one or more DC-balanced words to generate data signaling representative of one or more data words; and provide the data signaling to an output terminal.

Some embodiments include apparatuses and methods having a component to change a value of a bit among a number of M bits of information when the M bits have the same value and when M exceeds a selected value. At least one of such embodiments can include a transmitting component to provide the information to a connection. At least one of such embodiments can include a receiving component to receive the information from the connection. In at least one of such embodiments, the selected value can include a maximum number of consecutive bits having the same value that such a receiving component can be configured to receive. Other embodiments including additional apparatuses and methods are described.

Systems and methods for clock synchronization are disclosed in which a primary node generates special physical layer clock sync symbols from the output of a reference clock and inserts the clock sync symbols within a symbol stream to one or more secondary nodes. Upon receiving a symbol stream, a secondary node can extract the clock sync symbols from the stream to synchronize its local clock with the reference clock of the primary node. In particular, the clock sync symbols can be inserted into the symbol stream at any arbitrary symbol location, e.g., even between consecutive symbols of a symbol encoded data frame. The clock sync symbols can also replace some control symbols in the symbol stream, such as idle or comma symbols. Accordingly, the clock sync symbols can be inserted into a symbol stream at fixed intervals, irregular intervals, or at any arbitrary time for high resolution clock synchronization.

Some embodiments include apparatuses and methods having a component to change a value of a bit among a number of M bits of information when the M bits have the same value and when M exceeds a selected value. At least one of such embodiments can include a transmitting component to provide the information to a connection. At least one of such embodiments can include a receiving component to receive the information from the connection. In at least one of such embodiments, the selected value can include a maximum number of consecutive bits having the same value that such a receiving component can be configured to receive. Other embodiments including additional apparatuses and methods are described.

A high-speed serial interface (HSIF) for communicating between an analog front end (AFE) and a radio via a bi-directional serial bit connection for an OFDM device.

A data transmission method includes: obtaining Q first code block streams, wherein Q is an integer greater than 1, the coding type is M1/N1 bit coding, and one code block in the first code block stream comprises a synchronization header area of (N1−M1) bits and a non-synchronization one code block in the second code block stream comprises a synchronization header area of (N1−M1) bits and a non-synchronization header area of M1 bits, and a non-synchronization header area of a code block in the Q first code block streams is carried in a non-synchronization header area of a code block in the second code block stream. header area of M1 bits; and placing non-synchronization header areas of code blocks in the Q first code block streams into a to-be-sent second code block stream, wherein a coding type of the second code block stream is M1/N1 bit coding.