A method of transition encoding including: receiving a data packet having a packet size; identifying one or more forbidden patterns in the data packet; segmenting the data packet into a plurality of segments based on a location of the one or more forbidden patterns in the data packet; and encoding the plurality of segments by removing the one or more forbidden patterns, and appending position indicator bits according to positions of the segments in the data packet.

The present disclosure relates to a data transmission method, device, system, and display device. The method includes encoding clock training data to obtain two sets of encoded data corresponding to the clock training data and complementary to each other, sending a specified set of encoded data in the two sets of encoded data to a receiving end when positive and negative pins of the transmitting end and the receiving end are correspondingly connected, sending other set of coded data in the two sets of coded data than the specified set of encoded data to the receiving end when the positive and negative pins of the transmitting end and the receiving end are reversely connected. The receiving end may be configured to perform clock training according to the received encoded data.

Transmitter circuitry includes inversion circuitry, first transform circuitry, and selection circuitry. The inversion circuitry generates a first transformed data word by inverting one or more of a plurality of bits of a first data word. The first transform circuitry generates a second transformed data word by performing a first invertible operation on the first data word and a second data word. The selection circuitry selects one of the first data word, the first transformed data word, and the second transformed data word based on a first number of bit inversions between the first data word and the second data word, a second number of bit inversions between the first transformed data word and the second data word, and a third number of bit inversions between the second transformed data word and the second data word. The selection circuitry further outputs the selected data word.

There is disclosed integrated circuitry comprising having a bit receiving arrangement adapted for receiving, in parallel, a plurality of data bits, the bit receiving arrangement further being adapted for receiving a data bit inversion bit associated to the plurality of data bits, the data bit inversion bit being for indicating whether the bits of the plurality of data bits are inverted. The integrated circuitry also comprises has a bit inversion arrangement adapted for inverting the bits of the plurality of data bits based on a comparison between the received data bit inversion bit and an inversion estimate bit, the inversion estimate bit being determined based on the plurality of data bits. The disclosure also pertains to related methods and devices.

This application relates to an encoding method and apparatus, and a display apparatus. The encoding method includes encoding 8-bit data corresponding to a to-be-encoded byte of to-be-transmitted data into alternative 10-bit data, the to-be-transmitted data including at least one to-be-encoded byte, detecting whether the first-digit data of the alternative 10-bit data is the same as the previous-digit data adjacent to the first-digit data, when the to-be-encoded byte is not the first byte of the to-be-transmitted data, inverting the alternative 10-bit data to obtain target 10-bit data, when the numerical value of the first-digit data is the same as that of the previous-digit data, and determining the alternative 10-bit data as the target 10-bit data, when the numerical value of the first-digit data is different from that of the previous-digit data. The 8-bit data, the alternative 10-bit data and the target 10-bit data are binary data.

This application relates to an encoding method and apparatus, and a display apparatus. The encoding method includes encoding 8-bit data corresponding to a to-be-encoded byte of to-be-transmitted data into alternative 10-bit data, the to-be-transmitted data including at least one to-be-encoded byte, detecting whether the first-digit data of the alternative 10-bit data is the same as the previous-digit data adjacent to the first-digit data, when the to-be-encoded byte is not the first byte of the to-be-transmitted data, inverting the alternative 10-bit data to obtain target 10-bit data, when the numerical value of the first-digit data is the same as that of the previous-digit data, and determining the alternative 10-bit data as the target 10-bit data, when the numerical value of the first-digit data is different from that of the previous-digit data. The 8-bit data, the alternative 10-bit data and the target 10-bit data are binary data.

A data transmission circuit includes a data bus inversion encoding circuit configured to compare previous output data and current output data, invert or non-invert the current output data to control the number of data transitions; and transmitters configured to drive signal transmission lines based on outputs of the data bus inversion encoding circuit.

Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (noninverted signal) and a number and/or ratio of ones and zeros in an inverted version of the signal (inverted signal). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.

A method of performing multiple data bus inversion (DBI) and a memory device performing the method are provided. The multiple DBI includes first through third DBI operations, wherein the first DBI operation determines whether to perform data inversion on a first data inversion group in which MN data bits of a MN data bit structure are grouped and performs the data inversion on the first data inversion group, the second DBI operation determines whether to perform data inversion on second data inversion groups formed by grouping M data bits from among the MN data bits and performs the data inversion on the second data inversion groups, and the third DBI operation determines whether to perform data inversion on third data inversion groups formed by grouping N data bits from among the MN data bits and performs the data inversion on the third data inversion groups.

A data transmission circuit includes a data bus inversion encoding circuit configured to compare previous output data and current output data, invert or non-invert the current output data to control the number of data transitions; and transmitters configured to drive signal transmission lines based on outputs of the data bus inversion encoding circuit.