In a multicarrier communication system having a plurality of subchannels, a method and apparatus for supporting at least two applications. For example, the method includes associating at least a first application in a set of currently active applications with a first latency path, allocating at least one subchannel to the first latency path, and in response to a change in the set of currently active applications, allocating the at least one subchannel to a second latency path associated with a second application in the set of currently active applications and different from the first latency path.

A system and method for line coding of data. A serial transmitter includes a forward error correction encoding circuit followed by a bit conditioning circuit. The bit conditioning circuit counts the lengths of runs of consecutive identical digits and, when the count reaches a threshold, flips a bit. A serial receiver receives the data from the serial transmitter. The serial receiver includes a forward error correction decoding circuit, which re-flips bits flipped by the bit conditioning circuit of the serial transmitter.

Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (noninverted signal) and a number and/or ratio of ones and zeros in an inverted version of the signal (inverted signal). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.

In various embodiments, a system comprising a network interface, a processor, and a non-transient memory medium operatively coupled to the processor is disclosed. The memory medium is configured to store a plurality of instructions configured to program the processor to receive a digital bit stream, transform the digital bit stream to an encoded digital bit stream. The encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel, and any combination thereof, and provides the encoded digital bit stream to the network interface for transmission. A non-transitory computer-readable memory medium and a computer-implemented method also are disclosed.

When a data path includes CMOS circuitry, such circuitry may introduce jitter into the data signal. Embodiments are described in which additional data transitions are made to occur, and these additional data transitions may change the characteristics of the data frequency content transferred to the power supply so that such noise may be better filtered. This may have an effect of reducing jitter in the data signal. In one embodiment, a second data signal is generated to be a version of a first data signal with every second bit inverted. Second CMOS circuitry receives the second data signal in parallel to first CMOS circuitry receiving the first data signal. The first CMOS circuitry and the second CMOS circuitry are connected to a same power supply.

Systems and methods for low-power single-wire communication are provided. In some embodiments, a method of operation of a transmitter to transmit a data word to a receiver using low-power single-wire communication includes receiving the data word to be transmitted to the receiver. The method also includes encoding the data word to be transmitted in a Pulsed Index Communication (PIC) format to produce a PIC data word and transmitting the PIC data word to the receiver. In this way, the transmitter may be able to transmit an increased amount of data while maintaining a simple communication protocol that uses low power and does not require a Clock-Data Recovery circuit.

A method is provided for generating an efficiently transferable bit sequence with a limited disparity and a limited run length. A correspondingly configured system arrangement as well as to a computer program product and a memory-readable medium with control commands which execute the method are provided as well.

In various embodiments, a system comprising a network interface, a processor, and a non-transient memory medium operatively coupled to the processor is disclosed. The memory medium is configured to store a plurality of instructions configured to program the processor to receive a digital bit stream, transform the digital bit stream to an encoded digital bit stream. The encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel, and any combination thereof, and provides the encoded digital bit stream to the network interface for transmission. A non-transitory computer-readable memory medium and a computer-implemented method also are disclosed.

A method is provided for generating an efficiently transferable bit sequence with a limited disparity and a limited run length. A correspondingly configured system arrangement as well as to a computer program product and a memory-readable medium with control commands which execute the method are provided as well.

Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (noninverted signal) and a number and/or ratio of ones and zeros in an inverted version of the signal (inverted signal). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.