Patent classifications
H04L25/4919
Transmission device and communication system
A transmission device according to an embodiment of the present disclosure includes three output terminals that are arranged in one line and three sets of inductor elements and ESD protection elements that are provided for the respective output terminals. The three output terminals are respectively coupled to three transmission paths. The three sets of the inductor elements and the ESD protection elements are arranged in a non-orthogonal direction with respect to a direction in which the three output terminals are arranged. The transmission device further includes a driver circuit that outputs three actuation signals to the respective three output terminals through the respective three sets of the inductor elements and the ESD protection elements.
Multi-level balanced code for wireless communications
Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive data encoded based on a multi-level balanced code, codewords of the multi-level balanced code being selected based on a finite number of multiple sum values, corresponding to all constellation symbol sequences in the multi-level balanced code. The UE may receive a superimposed pilot (SIP) using communication resources occupied by the data. The UE may estimate one or more channel parameters based on the SIP and the multi-level balanced code. Numerous other aspects are described.
ENCODING METHOD, DECODING METHOD, TRANSMISSION METHOD, DECODING DEVICE, ENCODING DEVICE, TRANSMISSION DEVICE
The encoding method includes an encoding process of encoding a bit sequence to be transmitted, into a symbol sequence. The symbol sequence includes a plurality of symbols each having a signal level to which any one of 2.sup.n different values is allocated. n is an integer equal to or larger than 1. The encoding process includes encoding the bit sequence to be transmitted into the symbol sequence so that the symbol sequence does not include one or more prohibited patterns. The one or more prohibited patterns include one or more specific patterns which are one or more of patterns representing transition of signal levels of three or more consecutive symbols. The one or more specific patterns include one or more patterns in which signal levels of any two adjacent symbols of the three or more consecutive symbols are different values.
SERDES PRE-EQUALIZER HAVING ADAPTABLE PRESET COEFFICIENT REGISTERS
An illustrative SerDes (serializer-deserializer) communications method embodiment may include a transceiver: selecting one of multiple registers to specify initial pre-equalizer coefficient values; updating the initial pre-equalizer coefficient values during a training phase; and using the updated pre-equalizer coefficient values to convey a transmit data stream. In an illustrative embodiment of a chip-to-module communications link, a port connector couples a port transceiver to a pluggable module transceiver, the pluggable module transceiver including: one or more transmit filters to each pre-equalize a corresponding serial symbol stream being transmitted to the port transceiver; and a controller having multiple registers, each of the multiple registers containing a set of initial coefficient values, the controller using one of the registers to set initial coefficient values for the one or more transmit filters.
Low power chip-to-chip bidirectional communications
Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.
METHOD AND DEVICE FOR DATA TRANSMISSION WITH REDUCED SUPPLY NOISE
The disclosure relates to a pulse amplitude modulation (PAM) data encoding technique capable of reducing effects due to supply noise. A data transmission method according to an embodiment includes identifying an encoding rule of mapping a plurality of pieces of N-bit data and M data symbols, according to a designated level, obtaining a plurality of segmented pieces of data by performing segmentation on input data in units of N bits, mapping the obtained plurality of segmented pieces of data to the M data symbols based on the identified encoding rule, and transmitting the M data symbols obtained as a result of mapping through a plurality of single-ended data lines, wherein an absolute value of a sum of the M data symbols has a value equal to or less than the designated level.
Techniques for communicating multi-level signals
Methods, systems, and devices for techniques for communicating multi-level signals are described. A first device may be configured to communicate signals with a second device according to a modulation scheme. The first device may transmit a first signal to the second device at a first voltage level of the modulation scheme corresponding to a first multi-bit value. The first device may select a second voltage level of the modulation scheme based on a difference between the first voltage level and a third voltage level of the PAM scheme, and may transmit a second signal to the second device at the second voltage level to indicate a second multi-bit value corresponding to the third voltage level. The second device may decode the second signal to determine the second multi-bit value based on receiving the first signal at the first voltage level and the second signal at the second voltage level.
Synchronously-switched multi-input demodulating comparator
Methods and systems are described for obtaining a set of carrier-modulated symbols of a carrier-modulated codeword, each carrier-modulated symbol received via a respective wire of a plurality of wires of a multi-wire bus, applying each carrier-modulated symbol of the set of carrier-modulated symbols to a corresponding transistor of a set of transistors, the set of transistors further connected to a pair of output nodes according to a sub-channel vector of a plurality of mutually orthogonal sub-channel vectors, recovering a demodulation signal from the carrier-modulated symbols, and generating a demodulated sub-channel data output as a differential voltage on the pair of output nodes based on a linear combination of the set of carrier-modulated symbols by controlling conductivity of the set of transistors according to the demodulation signal.
TRANSMISSION DEVICE AND COMMUNICATION SYSTEM
A transmission device according to an embodiment of the present disclosure includes three output terminals that are arranged in one line and three sets of inductor elements and ESD protection elements that are provided for the respective output terminals. The three output terminals are respectively coupled to three transmission paths. The three sets of the inductor elements and the ESD protection elements are arranged in a non-orthogonal direction with respect to a direction in which the three output terminals are arranged. The transmission device further includes a driver circuit that outputs three actuation signals to the respective three output terminals through the respective three sets of the inductor elements and the ESD protection elements.
METHOD AND APPARATUS FOR LOW POWER CHIP-TO-CHIP COMMUNICATIONS WITH CONSTRAINED ISI RATIO
An efficient communications apparatus is described for a vector signaling code to transport data and optionally a clocking signal between integrated circuit devices. Methods of designing such apparatus and their associated codes based on a new metric herein called the ISI Ratio are described which permit higher communications speed, lower system power consumption, and reduced implementation complexity.