An efficient communications apparatus is described for a vector signaling code to transport data and optionally a clocking signal between integrated circuit devices. Methods of designing such apparatus and their associated codes based on a new metric herein called the ISI Ratio are described which permit higher communications speed, lower system power consumption, and reduced implementation complexity.

Methods and systems are described for obtaining a set of carrier-modulated symbols of a carrier-modulated codeword, each carrier-modulated symbol received via a respective wire of a plurality of wires of a multi-wire bus, applying each carrier-modulated symbol of the set of carrier-modulated symbols to a corresponding transistor of a set of transistors, the set of transistors further connected to a pair of output nodes according to a sub-channel vector of a plurality of mutually orthogonal sub-channel vectors, recovering a demodulation signal from the carrier-modulated symbols, and generating a demodulated sub-channel data output as a differential voltage on the pair of output nodes based on a linear combination of the set of carrier-modulated symbols by controlling conductivity of the set of transistors according to the demodulation signal.

Methods and systems are described for receiving signal elements corresponding to a first group of symbols of a vector signaling codeword over a first densely-routed wire group of a multi-wire bus at a first set of multi-input comparators (MICs), receiving signal elements corresponding to a second group of symbols of the vector signaling codeword over a second densely-routed wire group of the multi-wire bus at a second set of MICs, and receiving signal elements corresponding to the first and the second groups of symbols of the vector signaling codeword at a global MIC.

Vector signaling codes are synergistically combined with multi-level signaling, the increased alphabet size provided by the multi-level signaling enabling a larger codeword space for a given number of symbols, at the cost of reduced receiver detection margin for each of the multiple signal levels. Vector signaling code construction methods are disclosed in which code construction and selection of multi-level signal levels are coordinated with the design of an associated receive comparator network, wherein modified signal levels encoded and emitted by the transmitter result in increased detection margin at the receive comparators.

System and method indicating delays added to packets due to retransmission events. The method includes the steps of receiving multiple packet streams and multiplexing them into a first multiplexed packet stream; storing in memory the first multiplexed packet stream together with time indications; receiving a retransmission request and selecting data for retransmission; multiplexing the first multiplexed packet stream and the data for retransmission into a second multiplexed packet stream; utilizing the time indications for calculating delays that were added to packets of the second multiplexed packet stream as a result of fulfilling the retransmission request; adding the calculated delays to at least some of the packets of the second multiplexed packet stream; and transmitting the second multiplexed packet stream.

Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct but temporally aligned data and clocking signals over the same transport medium. Embodiments providing enhanced LPDDR interfaces are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.

Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.

A pair of ground planes arranged in parallel, a dielectric medium disposed in between the pair of ground planes, and a set of at least four signal conductors disposed in the dielectric medium, the set of at least four signal conductors having (i) a first pair of signal conductors arranged proximate to a first ground plane of the pair of ground planes and (ii) a second pair of signal conductors arranged proximate to a second ground plane of the pair of ground planes, each signal conductor of the set of at least four signal conductors configured to carry a respective signal corresponding to a symbol of a codeword of a vector signaling code.

Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

A data transmission and reception system may include: a data transmission apparatus configured to generate N Tx signals having discrete levels using N binary data, and output the N Tx signals to N single-ended signal lines, respectively, where N is a natural number equal to or larger than 2; and a data reception apparatus configured to receive the N Tx signals transmitted in parallel through the single-ended signal lines, and restore the N binary data by comparing the received N Tx signals to each other.