A differential detector for a receiver and a method of detecting the value of symbols of a signal is disclosed. In particular, a detector comprising: an analog to digital converter for sampling samples from symbols of a signal; a differentiator configured to differentiate the samples with a transfer function to produce a differentiated series of samples for each symbol; and a decision device configured to determine the value of each symbol by comparing values of the differentiated series of samples with boundary condition values.

A device is provided comprising a shared bus including a first and a second line, a first subset of devices and a second subset of devices coupled to the shared bus. The first subset of devices may be configured to operate according to a first protocol mode. The second subset of devices may be configured to operate according to a second protocol mode, wherein the second protocol mode is distinct from the first protocol mode. A first device within the first subset of devices may include a receiver circuit adapted to adjust a signal transition occurring on the first line while the second line is in a first logical state so that the signal transition instead occurs when the second line is in a second logical state. The signal transition is adjusted only if it occurs within a threshold amount of time from a second transition on the second line.

Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method for calibrating a clock recovery circuit includes recovering a first clock signal from transitions between pairs of symbols representative of successive signaling states of a 3-wire interface, where each pair of symbols includes a first symbol and a second symbol, generating a second clock signal by delaying the first clock signal by a first delay value, generating a third clock signal by delaying the second clock signal, calibrating the second clock signal and the third clock signal by initializing the first delay value such that the first sampling circuit, the second sampling circuit and the third sampling circuit capture the same symbol in a first pair of symbols, and incrementally increasing the first delay value until the second sampling circuit and the third sampling circuit capture different symbols from each pair of symbols.

A method and a transmitter for transmitting a pay load sequence are provided. The transmitter includes a ternary sequence mapper configured to map a binary data sequence to a ternary sequence stored in the transmitter, and a pulse shaping filter configured to generate a first signal based on the mapped ternary sequence. The ternary sequence includes elements of 1, 0, and 1.

A transmission line of the disclosure includes: a first line; a second line having characteristic impedance higher than characteristic impedance of the first line; and a third line. The transmission line transmits a symbol that corresponds to a combination of signals in the first line, the second line, and the third line.

A data transmission and reception system may include: a data transmission apparatus configured to generate N Tx signals having discrete levels using N binary data, and output the N Tx signals to N single-ended signal lines, respectively, where N is a natural number equal to or larger than 2; and a data reception apparatus configured to receive the N Tx signals transmitted in parallel through the single-ended signal lines, and restore the N binary data by comparing the received N Tx signals to each other.

Apparatus, systems and methods for improving coexistence on a multi-wire interface are disclosed. A method of transmitting data on a multi-wire interface includes providing a plurality of data bits in a word to be transmitted on the multi-wire interface, transcoding the word to be transmitted to obtain a first multi-digit ternary number representative of the numerical value of the word to be transmitted, inserting marker digits into the first multi-digit ternary number to obtain a second multi-digit ternary number, and generating a sequence of symbols. Each symbol in the sequence of symbols may be generated using a digit of the second multi-digit ternary number and a preceding symbol in the sequence of symbols. The preconfigured values and the preconfigured locations of the marker digits may be selected to prevent occurrence of I3C HDR Exit or HDR I3C Restart signaling when the sequence of symbols is transmitted on the multi-wire interface.

The present invention describes a method and system for simultaneous transmission of data to coherent and non-coherent receivers. The method at the transmitter includes retrieving a base ternary sequence having a pre-defined length, obtaining one or more ternary sequences corresponding to data to be transmitted and transmitting the obtained one or more ternary sequences by the transmitter. The method steps at the receiver includes receiving one or more ternary sequences corresponding to the data transmitted, demodulating each of the received ternary sequences by correlating with all cyclic shifts of the base ternary sequence by the receiver if the receiver is a coherent receiver, demodulating each of the received ternary sequences by correlating with all cyclic shifts of the absolute of the base ternary sequence by the receiver if the receiver is a non-coherent receiver and detecting the transmitted data based on the cyclic shifts corresponding to maximum correlation values.

An intelligent equalization technique is provided for a three-transmitter system in which mid-level transitions are selectively emphasized and de-emphasized to conserve power and reduce data jitter.

Apparatuses and methods for multi-level communication architectures are disclosed herein. An example apparatus may include a driver circuit configured to convert a plurality of bitstreams into a plurality of multilevel signals. A count of the plurality of bitstreams is greater than count of the plurality of multilevel signals. The driver circuit further configured to drive the plurality of multilevel signals onto a plurality of signal lines using individual drivers. A driver of the individual drivers is configured to drive more than two voltages.