A communication method and a system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT) are provided. The system may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The method includes receiving, from a base station, scheduling information for a first uplink packet transmission in a first time slot, determining whether the first uplink packet transmission in the first time slot is restricted based on information corresponding to a second uplink packet transmission in the first time slot of another terminal, and if the first uplink packet transmission in the first time slot is restricted, skipping the first uplink packet transmission in a first time slot.

Disclosed are a calibration method and a calibration circuit. The calibration method and the calibration circuit effectively calibrate the mismatches between the first signal path and the second signal path of a receiver by calibrating a plurality of tap coefficients of a finite impulse response filter configured in the second signal path and optimizing the tap coefficients. The calibration and optimization for the tap coefficients of the finite impulse response filter is according to differences between the electrical characteristics the analog-to-digital convertor and the LPF in the first signal path and differences between the analog-to-digital convertor and the LPF in the second signal path. These differences are obtained when the data reception has not yet started by the receiver (that is, when the receiver is working in a training mode).

This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.

Disclosed are a calibration method and a calibration circuit. The calibration method and the calibration circuit effectively calibrate the mismatches between the first signal path and the second signal path of a receiver by calibrating a plurality of tap coefficients of a finite impulse response filter configured in the second signal path and optimizing the tap coefficients. The calibration and optimization for the tap coefficients of the finite impulse response filter is according to differences between the electrical characteristics the analog-to-digital convertor and the LPF in the first signal path and differences between the analog-to-digital convertor and the LPF in the second signal path. These differences are obtained when the data reception has not yet started by the receiver (that is, when the receiver is working in a training mode).

This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.

A delay-locked loop (DLL) is provided that ensures that the phase outputs that are provided as inputs to the harmonic rejection mixer (HRM) are sufficiently accurate to allow the HRM to effectively cancel out the spurious harmonic frequencies, thereby improving HRM parameters. The phase detector of the DLL can be programmable to provide a knob that can be used post layout to adjust the output phase differences of the DLL to make them more precise. This feature overcomes issues with mismatches in silicon that in the past have affected the ability of the DLL to settle precisely to the desired phases. This, in turn, loosens design and manufacturing constraints that are currently employed to ensure that the DLLs settle precisely to the desired phases. Additionally, logic gates are eliminated from the phase detector and replaced with resistors to reduce current consumption and further looser design and manufacturing constraints.

According to an aspect, there is provided a method for transmitting a low-power radio signal, comprising: transmitting, by a radio device, a data radio signal by using binary frequency-shift-keying modulation introducing a phase change between consecutive bit intervals in the data radio signal; and transmitting, by the radio device, a wake-up radio signal using the binary frequency-shift-keying modulation where repetition coding is applied before the frequency-shift-keying to eliminate the phase change between consecutive bit intervals in the wake-up radio signal.

A delay-locked loop (DLL) is provided that ensures that the phase outputs that are provided as inputs to the harmonic rejection mixer (HRM) are sufficiently accurate to allow the HRM to effectively cancel out the spurious harmonic frequencies, thereby improving HRM parameters. The phase detector of the DLL can be programmable to provide a knob that can be used post layout to adjust the output phase differences of the DLL to make them more precise. This feature overcomes issues with mismatches in silicon that in the past have affected the ability of the DLL to settle precisely to the desired phases. This, in turn, loosens design and manufacturing constraints that are currently employed to ensure that the DLLs settle precisely to the desired phases. Additionally, logic gates are eliminated from the phase detector and replaced with resistors to reduce current consumption and further looser design and manufacturing constraints.

A digital calibration device for an RF-system includes a first input to receive I-channel data and a second input to receive Q-channel data; a first filter coupled to the first input and configured to estimate a DC offset of the I-channel data and to subtract the DC offset from the I-channel data to provide filtered I-channel data; and a second filter coupled to the second input and configured to estimate a DC offset of the Q-channel data and to subtract the DC offset from the Q-channel data to provide filtered Q-channel data. The device includes a combining element configured to provide a specified magnitude value (adc_data_iq) based on the filtered I- and Q-channel data; and a level detector configured to receive the magnitude value of the filtered I-channel data and Q-channel data and to provide a filter coefficient for the first and second filters depending on the magnitude value.