H04L27/2272

High frequency wireless power transmission system

Described herein are embodiments of apparatuses and methods a wireless power transmission system (WPTS) receiving encoded beacon information from a wireless power receiver client (WPRC) and transmitting focused, directional wireless power to the WPRC.

TIME TO DIGITAL CONVERTER WITH INCREASED RANGE AND SENSITIVITY
20200110369 · 2020-04-09 ·

Systems and methods are described for determining a phase measurement difference between a received modulated signal and a local clock signal. An adjusted local clock phase measurement may be determined by subtracting, from the phase measurement difference, a phase correction that is based on the frequency difference between the modulator signal's carrier frequency and the local clock's frequency. A phase modulation value may be generated by scaling the adjusted local clock phase measurement. The scaling may be based on a ratio of the modulated signal's carrier frequency and the local clock's frequency. The phase correction may be based on (i) a count of periods of the modulated signal occurring between each corrected phase measurement and (ii) a difference between the carrier frequency and the local clock frequency.

Spectrum analyzer using multiple intermediate frequencies and multiple clock configurations for residual, spurious and image signal reduction
10564198 · 2020-02-18 · ·

A method for spurious signal reduction when measuring a spectrum of a radio frequency signal over a frequency span. The radio frequency signal is converted to a sequence of intermediate frequency signals using a sequence of local oscillator signals each having a different frequency. The sequence of intermediate frequency signals are converted to a sequence of digitized intermediate frequency signal sample sets, each set having a frequency value and a signal energy value. The frequency span is divided into frequency sample bins. For each frequency sample bin, all frequency domain samples from the sequence of frequency domain sample sets having a frequency value within the frequency sample bin are associated with that sample bin. For each frequency sample bin, of the frequency domain samples associated with that frequency bin, the frequency domain sample having the signal energy value that is lowest is selected for a combined frequency domain sample set.

CARRIER RECOVERY ANALOG SYSTEM FOR A RECEIVER OF A N-PSK SIGNAL

A carrier recovery system for a receiver of a phase-modulated signal N-PSK, the system including a first pre-conditioning circuit of the signal received (S(t)), with the pre-conditioned signal (SP(t)) having a component, non-modulated in phase, at the frequency N.sub.c where .sub.c is the carrier used for the modulation N-PSK, and a carrier regeneration circuit to regenerate two sinusoidal signals in quadrature at the frequency .sub.c, with these signals being phase locked with respect to said non-modulated component in phase of the pre-conditioned signal.

Optical signal reception apparatus, optical communication system, and method of generating compensation signal of optical signal reception apparatus
10530489 · 2020-01-07 · ·

A frequency difference compensation unit (510) generates a carrier recovery signal by compensating for a frequency difference between a local light beam and an optical signal in a plurality of digital signals. A first symbol determination unit (521) determines the symbol position of the carrier recovery signal in which a frequency difference is compensated for, in accordance with the signal arrangement of multi-value modulation. A second symbol determination unit (522) determines the symbol position of the carrier recovery signal in which a frequency difference is compensated for, in accordance with a signal arrangement in which the number of multi-values of the multi-value modulation is reduced. A loop filter unit (540) and a compensation signal generation unit (550) temporarily generates a compensation signal using a determination result of the second symbol determination unit (522), and then regularly generates the compensation signal using a determination result of the first symbol determination unit (521).

Serializer/Deserializer (SerDes) Lanes with Lane-by-Lane Datarate Independence
20200007305 · 2020-01-02 ·

A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.

MULTI-LEVEL SIGNAL CLOCK AND DATA RECOVERY
20200007133 · 2020-01-02 ·

A system for retiming a multi-level signal that forms an eye diagram when plotted, such as a PAM4 signal that includes an equalizer configured to create an equalized signal and a first amplifier configured to amplify the equalized signal, responsive to a first amplifier control signal, to create a first amplified signal, and a second amplifier configured to amplify the equalized signal, responsive to a second amplifier control signal, to create a second amplified signal. An eye monitor processes the equalized signal, the first amplified signal, and the second amplified signal to create a first retiming clock phase signal and a second retiming clock phase signal, which control sampling times for flip-flops. One or more delays and one or more emphasis modules are configured to delay and introduce emphasis into an output from the flip-flops, the resulting signals are combined in a summing junction to create the retimed signal.

Time to digital converter with increased range and sensitivity
10503122 · 2019-12-10 · ·

Systems and methods are described for determining a phase measurement difference between a received modulated signal and a local clock signal. An adjusted local clock phase measurement may be determined by subtracting, from the phase measurement difference, a phase correction that is based on the frequency difference between the modulator signal's carrier frequency and the local clock's frequency. A phase modulation value may be generated by scaling the adjusted local clock phase measurement. The scaling may be based on a ratio of the modulated signal's carrier frequency and the local clock's frequency. The phase correction may be based on (i) a count of periods of the modulated signal occurring between each corrected phase measurement and (ii) a difference between the carrier frequency and the local clock frequency.

HIGH FREQUENCY WIRELESS POWER TRANSMISSION SYSTEM

Described herein are embodiments of apparatuses and methods a wireless power transmission system (WPTS) receiving encoded beacon information from a wireless power receiver client (WPRC) and transmitting focused, directional wireless power to the WPRC.

Serializer/deserializer (SerDes) lanes with lane-by-lane datarate independence
10461917 · 2019-10-29 · ·

A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.