The disclosure relates to a communication technique and a system for converging a fifth generation (5G) and subsequent communication system with Internet of things (IoT) technology to support a higher data transmission rate than a fourth generation (4G) system. The disclosure is applied to the intelligent service based on the 5G and subsequent communication technology and IoT-related technology. The reception device according to the disclosure receives orthogonal frequency division multiplexing (OFDM) signals through a plurality of antennas, aligns the received OFDM signals, converts at least one of the aligned reception signals into a designated symbol, estimates the data symbols of the reception signals based on the designated condition, and determines the data symbol of the reception signals by synthesizing at least one of the converted reception signals among the estimated reception signals.

A method for generating clock signals includes dividing an input clock signal to obtain a first in-phase output clock signal, dividing an inverted version of the input clock signal to obtain a first quadrature output clock signal, delaying edges in the input clock signal to obtain a second quadrature output clock signal, selecting a full-rate output to provide a multiphase output clock in a first mode of operation, and selecting a half-rate output to provide the multiphase output clock in a second mode of operation. The first quadrature output clock signal is a quadrature version of the first in-phase output clock signal. The first in-phase output clock signal and the first quadrature output clock signal are included in the full-rate output. The second quadrature output clock signal is included in the half-rate output and is a quadrature version of the input clock signal.

A receiver apparatus for receiving an OFDM radio signal comprising a first plurality of subcarrier-symbols, modulated on a corresponding plurality of subcarriers, and a second plurality of subcarrier-symbols, modulated on the corresponding plurality of subcarriers, to generate first and second bit sequences, the first bit sequence being an interleaved version of the second bit sequence according to a predetermined interleave function. Soft-output decoder logic generates a first soft-bit sequence for the first plurality of subcarrier-symbols, and a second soft-bit sequence for the second plurality of subcarrier-symbols. Combiner logic combines the soft-bit sequences, with the soft-bit sequences either both in an interleaved state or both in a non-interleaved state, by combining a respective soft-bit having a bit position in the first soft-bit sequence with a respective soft-bit having a same bit position in the second soft-bit sequence. Hard-output decoder logic outputs a hard-bit sequence representing the transmitted bit sequence.